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* Register FFDC call is handled within machine_check_handlerRaja Das2018-01-191-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Within the PK interrupt vector, if you have a function call from one function to another, it needs branch link instruction, but since the BL is already being used to jump from software context to the PK Vectored Interrupt context, the function call from within will corrupt the Link register. For interrupts like data_storage, instruction_storage, alignment_exception and program_exception, the save-off will capture the LR registers to indicate which interrupt was getting executed when halt happened. For Machine check handler, LR won't be valid. Change-Id: Iee17b37acd438c7bee2c956cac2de3ce64d04441 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51587 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51588
* Fix three NDD2.1 dials and add new NDD2.2 workaroundsNick Klazynski2018-01-171-14/+189
| | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I0d0aebc925c963a32e2cf2266e833df84a799235 CQ: HW409194 CQ: HW407065 CQ: HW419541 CQ: HW430944 CQ: HW417829 CQ: HW422533 CQ: HW414249 CQ: HW432749 CQ: HW414146 CQ: HW433125 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51677 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51685 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Zepplin:Remove dd level check for cumulus under PPB codePrasad Bg Ranganath2018-01-141-7/+0
| | | | | | | | | | | | | | | Change-Id: I5435bef91381ade76a1439a842fa90b86e17aab3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51599 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51604 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add FABRIC_PRESENT_GROUPS system attributeChristian Geddes2018-01-141-1/+17
| | | | | | | | | | | | | | | | | | Bit mask of group IDs which will be present in the fully configured CEC configuration. Change-Id: I43b06e856d2b285bb919025926b914d3ec4de451 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51692 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51701 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Ignore allow_reg_wakeup in cache contained modeBrian Vanderpool2018-01-141-0/+28
| | | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: If2916c99b37c4ce56ad1cf6f6957d67497fac5ab CQ: SW412668 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51394 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Dev-Ready: Brian T. Vanderpool <vanderp@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51471 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Workaround for Quaint Gate, Angry ReindeerJenny Huynh2018-01-141-4/+29
| | | | | | | | | | | | | | | | | Change-Id: Iee18d460dc99de59eb0b1f8891dad1e8698e3208 CQ:HW430944 CQ:HW432070 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51370 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51428 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* xip_customize and TOR API: Improved DD level verificationClaus Michael Olsen2018-01-145-22/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | This update propagates the extracted EC level in xip_customize through to the TOR API via the call to tor_get_single_ring(). The TOR API has been updated to verify that the requested DD level matches matches the DD level in the TOR header of the supplied ring section which, in the case of xip_customize, is an .overlays ring section. Key_Cronus_Test=XIP_REGRESS Change-Id: Ic087c269306acc0afcb8c759fe68eac63ae93d29 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51339 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51349 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* jgr171017 Setting changes for Obus boardwire vs cableJohn Rell2018-01-141-0/+24
| | | | | | | | | | | | | | | | Change-Id: I6c64841173f036c4898c199ef1615046a3974dcc CQ: HW422471 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48525 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50964 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Large update for securityNick Klazynski2018-01-141-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | | - IMC6 changed to implement special nop - IMC7 serializes bcctr for NDD2.2/CDD1.1 - mttrig2 moved to mttrig0 - mttrig2 now causes an L1 flush on NDD2.2/CDD1.1 - Force private L1D - branch hint bits always honored - enable new TM mode for NDD2.2 Change-Id: I3b724f6d742b9ba321ea1abbfa6bbc7d5482b8ed CQ: HW430733 CQ: SW410726 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50872 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51025 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disable read data delay for Cumulus DD1.0, enable for DD1.1Joe McGill2018-01-141-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | centaur.mbs.scan.initfile Remove static application of read data delay disables Centaur will now flush to read data delay enabled cen_initf Add block to re-rotate tcn_mbs_func and: - fix existing spy parity errors - apply read data delay disables, executed only when attached chip is Cumulus DD1.0 Change-Id: I10279decbbf27df911a94ce27d11b4d2e30b6e5f RTC: 138785 CQ: HW419021 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50720 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50735 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_chiplet_reset: Remove SIM_ONLY conditional around delayJoachim Fenkes2018-01-131-3/+1
| | | | | | | | | | | | | | | | | That delay was always compiled into the procedure and we tested with it, so let's make it permanent. Change-Id: If8a5c6fbf4bd8b42e37656f66ced96604813485b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48748 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48754 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* apply rings from Centaur HW imageJoe McGill2018-01-133-109/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cen_ringId.CH cen_ring_id.h add entries to hold multiple PLL rings, 8 in total cen_initf.C cen_pll_initf.C cen_pll_initf_errors.xml replace invocation of generated initfile HWP with putRing API calls (rings to be scanned gleamed from p8 cen assembly source) select correct PLL ring image based on NEST,MEM frequency cen_bucketX.txt define frequency points for each PLL bucket 1 = 2000 MHz NEST, 1066 MHz MEM 2 = 2000 MHz NEST, 1333 MHz MEM 3 = 2000 MHz NEST, 1600 MHz MEM 4 = 2000 MHz NEST, 1866 MHz MEM 5 = 2400 MHz NEST, 1066 MHz MEM 6 = 2400 MHz NEST, 1333 MHz MEM 7 = 2400 MHz NEST, 1600 MHz MEM 8 = 2400 MHz NEST, 1866 MHz MEM ipl_base.txt ipl_risk.txt remove frequency attributes from base attribute files scan_procedures.mk add rules to generate PLL buckets Change-Id: I8aee5e82337800ea9afe9a9af12d8d34f6e1e01e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50475 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50478 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Workaround for Warlike Parasite (HW430546)Lennard Streat2018-01-131-0/+18
| | | | | | | | | | | | | | | | Change-Id: I1c93a9b505e6656ea9bda20a7fac363e037a3d73 CQ: HW430546 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50832 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50979 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* fix ADU setup for MCD disabled operationJoe McGill2018-01-131-2/+2
| | | | | | | | | | | | | | Change-Id: I0068d797ad4a82216e440f701c5182ad95584a15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51503 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51504 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_build_smp -- use ADU chipops to switch fabric configuration part #1Thi Tran2018-01-134-21/+124
| | | | | | | | | | | | | | | | | | This commit is the first part of 49692, which is splitted in order to have SBE platform proceed with code supports. Change-Id: I1f491cac6cfef8476487217067d69d4551de1228 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51048 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51049 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Overlays and multi-DD XIP related updates to xip_image and dd_containerClaus Michael Olsen2018-01-131-19/+23
| | | | | | | | | | | | | | | | | | | | | | to support WIN32 for manu team. Also, - various updates to dd_container error handling, - improved DD support query checking. Change-Id: I2eab02732b3852698d8ffba5eed16a5e0bb37faa Original-Change-Id: I706e56258894c3453cf01aa1a637fe888af1db00 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46596 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51558 Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3: Honor PCI osc selection when checking for osc errorsJoachim Fenkes2018-01-121-8/+12
| | | | | | | | | | | | | | | | | | | | The PCI oscillator checking code in proc_clock_test2 always checked both osc error bits, which fails on a Cumulus system with only a single PCI refclock active. Modify it to check osc error bits depending on which oscillators have been configured in the osclite config. Change-Id: I8c5ee38f8bc718dbb8eab59139a19800bb3a9f6f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51723 Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martin Padeffke <padeffke@de.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51796 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* MCD disable workaround for HW423589 (option1)Joe McGill2018-01-124-5/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need MCD disable for HW423589 (applied to Nimbus EC20 and 22+) p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scan.initfile p9.l3.scan.initfile p9.mmu.scom.initfile p9.ncu.scan.initfile p9.npu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_pcie_config.C set unit scope disable dials p9_sbe_scominit.C p9_pm_pba_init.C set PBA unit scope disable dial p9_pm_set_homer_bar.C change PBA0 default command scope from GROUP to NODAL p9.fbc.ab_hp.scom.initfile disable group master setup p9_setup_bars.C p9_setup_bars_defs.H skip MCD setup for HW423589_OPTION1 cmvc-prereq: 1043014 Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SW410723 chiplet ID range for address 107D0 is increased to 0x37.Sunil Kumar2018-01-121-1/+1
| | | | | | | | | | | | | | Change-Id: I05b7b14e8ce7fdb61be1a5e6ccefc2e49beeeb4f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51236 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51239 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Solve compilation issue for type castingSachin Gupta2018-01-101-2/+2
| | | | | | | | | | | | | | Change-Id: If9ce191a8d09ccf4cd46fd9daabb26bfe8012fef Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45780 Reviewed-by: ARAVIND T. NAIR <aravindnair@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Srikantha S. Meesala <srikantha@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51522 Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_dd_container: simple generic standalone DD level containerMartin Peschke2018-01-081-0/+262
| | | | | | | | | | | | | Change-Id: I4245ba11c525e8406cf24554b2c0194c8023c13d Original-Change-Id: I4c9d8cb28d4ae6a8b21c87ebaad07c1fd7163b85 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39588 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Martin Peschke <mpeschke@de.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51557 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding CT_P9A to the enum list of chip types.Claus Michael Olsen2018-01-031-5/+6
| | | | | | | | | | | | | | | | | | | | I inserted P9A before CT_CEN for purely estaetic reasons. Since the current Centaur image in EKB isn't being used yet, this should be safe (as otherwise there would be a co-req situation). Change-Id: Ia5ef9950644eacea3fdc28a0195502bdcae44327 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50812 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50962 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PGPE: Fix FIT and actuation step conflictRahul Batra2017-12-201-1/+1
| | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I8cf51a4e044c70871c5f74a5d3a6ecfe64dafd47 CQ: SW411044 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50779 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50992 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* disable ECC bypass for Cumulus DD1.0Joe McGill2017-12-193-3/+28
| | | | | | | | | | | | | | | | | | | | | Nimbus DD2.0 disable will go into op910 only (for Boston Coral) but not into master Change-Id: I28376316be3e6700af97df83a02c48e46d715dec CQ: HW415945 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50445 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50453 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Increase cache data timeout valuesLuke C. Murray2017-12-153-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | The PCIe timeout have increased to 66-100ms, so we need to double the NCU master timeouts to be above these timeouts. This has a chain effect causing the L2/L3 master timeouts to increase which causes the tlbie snooper to increase which causes the tlbie master to increase. This would also ususally cause the core timeout to increas, but the core is already at around 13 seconds, so there is headroom there. Change-Id: I5930076151267a9bfa66e24edef0985c165db0b7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50582 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50602 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP/PState: SGPE/PGPE Error Handling SupportYue Du2017-12-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon PGPE Halt 1) SGPE performs STOP Recovery Trigger to set a malfunction alert and removes PGPE IPCs from wake-up decisions. 2) CME is interrupted by QPPM OCC Heartbeat Lost that PGPE stopped updating Upon SGPE Halt 1) PGPE moves to Psafe 2) PGPE performs STOP Recovery Trigger to set a malfunction alert. This commit also includes SGPE Panic Code Cleanup such as debug halt support. However PGPE Panic Code Cleanup is dealt in a different commit Key_Cronus_Test=PM_REGRESS Change-Id: I893aa1ef21d2f684722b8c10dbbeb92b9505c1c4 CQ: SW410252 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49275 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49429 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PPE: Adjust the maximum decrementer countDoug Gilbert2017-12-151-2/+5
| | | | | | | | | | | | | | | | Change-Id: I4f59cabf7439590ac736e6f64e35acf11e6c5aa9 CQ: SW402715 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46944 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46950 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Expand PGPE optrace to Main Mem - No fnctl coreq rqmt image build vs hcodeAdam Hale2017-12-151-2/+1
| | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I823b350ffe1e07108fbadd4b0456c7188839932f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46480 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48106 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove writable property from ATTR_LINK_TRAINChristian Geddes2017-12-151-1/+0
| | | | | | | | | | | | | | | | | | This attribute was both platInit and writable, that should not be the case. After talking w/ HW guys Change-Id: I9d12581cf2772715693e8b0a8dc539aeff87cc85 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50908 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50912 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Security: add AVSBus bridge registers to whitelistGreg Still2017-12-151-0/+24
| | | | | | | | | | | | | | | | | | | | - In order to set VDN voltages across the Master->Slave FSI links from Hostboot prior to XBus training, the AVSBus bridge registers have to be accessible through the SBE. - While the present code uses only the AVSBus O2S "B" bridge, both A and B bridge addresses are added so as to not be limiting in the future. The bridges are identical and are present to allow for Firmware separation. Change-Id: Ib702c2e49a2533deb4b2898cd533faab349ddf5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50657 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50662 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Removing P9_XIP_ITEM_NOT_FOUND trace out msg from p9_xip_image.CClaus Michael Olsen2017-12-151-2/+2
| | | | | | | | | | | | | | | | Change-Id: I72d3649a173fecee990c7ec1793568675be6c53d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50831 Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50837 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "Adding p9a support."Jennifer A. Stofer2017-12-145-180/+34
| | | | | | | | | | | | | | This reverts commit 41352b2d444e98639eedc06b1eb0d8da89d4adb3. Change-Id: Ic3f2099eff3f5c942ef8fb6916e8ee78ca1a9e82 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50703 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50722 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove writeable tag from ATTR_PROC_FABRIC_GROUP_IDSantosh Puranik2017-12-141-4/+0
| | | | | | | | | | | | | | | Change-Id: I94211977e9eca2d26a929d59fb4d582cbcfefb61 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50746 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50750 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Add Fallback Frequency for #V Bucket SelectionDan Crowell2017-12-121-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | Created ATTR_FREQ_PB_MHZ_POUNDV_FALLBACK to handle a few cases where modules were created with invalid #V for the frequency we would like to run them at. The code will use the real powerbus frequency to find the #V bucket (no change from current behavior) but will fall back to the new attribute if no matches are found. Change-Id: Ie15190ac092ca797a8a51d41eece7c4cd2d0f136 CQ: SW410357 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50677 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50682 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* support customized application of filter PLL buckets from AW MVPD keywordJoe McGill2017-12-126-20/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pervasive_attributes.xml sbe_attributes.xml create ATTR_FILTER_PLL_BUCKET to encapsulate BGoffset selection p9.filter.pll.overlay.scan.initfile generate correct BGoffset value based on ATTR_FILTER_PLL_BUCKET value build must process 4x (ATTR values 1..4) to generate set of ring images p9_xip_customize.C consume AW keyword from MVPD, set ATTR_FILTER_PLL_BUCKET for HB platform and customize into SBE image if attribute is present in image p9_sbe_npll_initf.C p9_sbe_npll_initf_errors.xml re-scan perv_pll_bndy ring with selected BGoffset overlay when ATTR_fILTER_PLL_BUCKET is non-zero p9_sbe_chiplet_pll_initf.C p9_sbe_chiplet_pll_initf_errors.xml adapt to error XML updates in p9_sbe_npll_initf Change-Id: Id09074d12e95ffc44337e32ec683056d8ec390f3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49442 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49460 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lock"Sachin Gupta2017-12-122-95/+3
| | | | | | | | | | | | | | | | This reverts commit 702e418be9ace793c323710411c2ca6b4d032c58. Change-Id: Iebbea4e980a974a10a46345262bd475e3e340771 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50800 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50802 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_npll_setup: Enable Spread Spectrum right after SS PLL lockJoachim Fenkes2017-12-112-3/+95
| | | | | | | | | | | | | | | | | | | | | | | | | As it is no longer a requirement that Spread Spectrum is enabled on all SS PLLs in a system in unison, we're better off turning on spreading as early as possible, so any link training runs off of a spread clock. The only way to enable Spread Spectrum in P9 is via the TOD Timer, so we have to set up a timer compare value of 1 and force the TOD value to 1 so that the timer is hit and the TOD's spread enable output turns on. Change-Id: I0bcd33f17ef06beafb44ba6777d32b98d0680deb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49662 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49667 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enhance SBE Deadman FFDC Format and sequencingAmit Tendolkar2017-12-115-70/+86
| | | | | | | | | | | | | | | | | | | | | | | | | 1. align data per FFDC member names 2. set the atomic lock FFDC so that errl parser works 3. collect sibling core data if in fused mode 4. do not collect ffdc on check_master_stop15 fails, as SBE will do that upon a chip-op request See https://ralgit01.raleigh.ibm.com/gerrit1/#/c/49473 for FW changes Change-Id: I9880cdd3480c84c418b662fb7174291ed7b68cdd RTC: 179364 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50648 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50653 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PGPE: STOP11+WOF+SafeMode FixesRahul Batra2017-12-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | -STOP11+WOF Fix -STOP11+WOF+Safe Mode Key_Cronus_Test=PM_REGRESS Change-Id: I7aae651213174049fa4fe89d6ac92fda2478e90a CQ: SW410652 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48989 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49320 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding p9a support.Ben Gass2017-12-095-34/+180
| | | | | | | | | | | | | | | | | | | Adding CTEPERLPATH to ENV-setup Jenkins failure CQ SW40996 Change-Id: I02a9c5f31fb0545e8f8c8cd99b528a467ae52cf8 CQ: SW409966 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45266 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50688 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enabling L2 64B store predictionLuke C. Murray2017-12-091-0/+17
| | | | | | | | | | | | | | | | | | Turning on the 64B store prediction inside the L2. This is a performance fix. Change-Id: I2e91747e2cf420ffa50efeb73b8876e54c89b8d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50531 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50542 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.npu.scom.initfile -- fix cq_sm allocation issue at low water markRyan Black2017-12-091-0/+24
| | | | | | | | | | | | | | | | Change-Id: Ibf7f3276279e99e82841d2a209230ce38081c419 CQ: HW426816 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50480 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50607 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Nimbus DD2.2 core chickenswitchesNick Klazynski2017-12-091-1/+136
| | | | | | | | | | | | | | | Change-Id: I209bf1735b7107303bbd9009d7c99201809ba8bf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50315 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50337 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Increase suspend_powman timeouts from 10 micro sec -> 10 milli secChristian Geddes2017-12-091-6/+9
| | | | | | | | | | | | | | | | | | Our timeouts for suspend_powman were way to short. This commit increases the timeouts by a factor of 1000. Per request from M. Floyd on PM team. Change-Id: I03c6e452a453979128d232c33d31ff9fd9dfbe6b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50470 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50474 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Override filter ring support for perv_pll_bndy_bucket rings.Claus Michael Olsen2017-12-094-4/+27
| | | | | | | | | | | | | | | | Change-Id: If1d4649da6da3c0d9e09ef4169d4181a1dc43bde Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49438 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49450 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cache/Core stop clocks: add shut down of Power Management to remove contentionsAmit Tendolkar2017-12-078-50/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ported changes from https://ralgit01.raleigh.ibm.com/gerrit1/#/c/44781/25 to simplify auto mirror conflicts and reuse existing SBE HWP files - Halt SGPE, PGPE and CMEs assocatiated within the targeted EQ - Clear the PCB atomic lock that may be in place by SGPE - Add core stopclocks changes - Fixed cache stop clocks XML callout - Fix atomic lock library dependencies - Only enable function on DD2 - Halt PPE only if not already in halt - Enhance PPE Halt FFDC Key_Cronus_Test=PM_REGRESS Change-Id: Id6c11176d222213bf1a01b91cade41de989f04c6 RTC: 180317 CQ: SW406569 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50415 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50420 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP Recovery: Only XIR collection in HWP error path during PM Reset.Prem Shanker Jha2017-12-071-0/+14
| | | | | | | | | | | | | | | | | CQ: SW406487 Change-Id: I97a0309261c4d3f257ade2b70d952be253dc8f65 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47124 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47128 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updated PSI and TOD regs into whitelistSrikantha Meesala2017-12-071-0/+7
| | | | | | | | | | | | | Change-Id: I5b8afde659b1c9f7c4f527791efaafb88e03380b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50482 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50487 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Adding attribute to turn memory early data onLuke C. Murray2017-12-054-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Performance wants a way to turn memory early data on & off using just scoms. Adding one attribute to control all the needed scoms and defaulting everything so that early data is off. For the L3 disable cp_me by default using scom Changing the scom cp_me dial to disable cp_me for all systems after Nimbus DD2.0. This is expected to be the correct setup for most systems. We didn't disable the cp_me at the scan, because the scom can only disable cp_me if ON or allow the scan setting if set OFF. Some systems might want cp_me enabled by only changing a scom. So the default is to set cp_me on at the scan and off a the scom. This way only the scom has to be turned off to enable cp_me. Also update three scoms in the memory controler that are needed for early data. Change-Id: Ib2106ec4b7d26cb084601f2d6eee68833b36d30b CQ: HW426419 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49261 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49331 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Code restruct: TOR APIClaus Michael Olsen2017-12-0412-1590/+717
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key_Cronus_Test=XIP_REGRESS Code restructuring aiming at: - utilizing TOR magic header info - enforce a common approach for - extracting metadata for all image,chipType combinations - traversing images for all image,chipType combinations - shrinking code size by reusing common code segments - improve readability by - separating more clearly metadata extraction and image traversal - slight rearrange of certain code segments - remove leftover hardcoded assumptions about ring/TOR data and structs - variables appropriately renamed and now all using camel style Change-Id: I50ace8b2fdb340a97ce6d74ce545c5e1acd21c40 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38863 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: GIRISANKAR PAULRAJ <gpaulraj@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43250 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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