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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2017-10-24 18:01:38 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-01-13 22:07:43 -0500 |
| commit | ac2deccdd5c7ff00492eccac80475f47fc0260a1 (patch) | |
| tree | 2ffa49726b16be162c6a141b45fc1db5c19d0ebd /src/import | |
| parent | 7d85e24ccf7d16ce4ee37d2e5092bb0fc51b60ed (diff) | |
| download | talos-sbe-ac2deccdd5c7ff00492eccac80475f47fc0260a1.tar.gz talos-sbe-ac2deccdd5c7ff00492eccac80475f47fc0260a1.zip | |
p9_sbe_chiplet_reset: Remove SIM_ONLY conditional around delay
That delay was always compiled into the procedure and we tested with
it, so let's make it permanent.
Change-Id: If8a5c6fbf4bd8b42e37656f66ced96604813485b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48748
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48754
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index db977093..77ff5a12 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -1483,9 +1483,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0( FAPI_DBG("Force PLL out enable for PLLs"); FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data)); -#ifdef SIM_ONLY_DELAY fapi2::delay(10000, (40 * 400)); -#endif l_data.flush<1>(); l_data.clearBit<PERV_1_NET_CTRL0_PCB_EP_RESET>(); |
