diff options
| author | Greg Still <stillgs@us.ibm.com> | 2017-12-07 13:03:40 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-12-15 00:57:02 -0500 |
| commit | 77f320df44110ba57aafbce747480e14baead297 (patch) | |
| tree | e2c6d0b1fd9e64882b7c709ec1e3ee2849d21192 /src/import | |
| parent | 4640d0953dd6f815f52f485762c573c601fd564f (diff) | |
| download | talos-sbe-77f320df44110ba57aafbce747480e14baead297.tar.gz talos-sbe-77f320df44110ba57aafbce747480e14baead297.zip | |
Security: add AVSBus bridge registers to whitelist
- In order to set VDN voltages across the Master->Slave FSI links from Hostboot
prior to XBus training, the AVSBus bridge registers have to be accessible
through the SBE.
- While the present code uses only the AVSBus O2S "B" bridge, both A and B
bridge addresses are added so as to not be limiting in the future. The
bridges are identical and are present to allow for Firmware separation.
Change-Id: Ib702c2e49a2533deb4b2898cd533faab349ddf5c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50657
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50662
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/security/p9_security_white_black_list.csv | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/import/chips/p9/security/p9_security_white_black_list.csv b/src/import/chips/p9/security/p9_security_white_black_list.csv index 24524a87..c08ae7c3 100644 --- a/src/import/chips/p9/security/p9_security_white_black_list.csv +++ b/src/import/chips/p9/security/p9_security_white_black_list.csv @@ -881,4 +881,28 @@ Version,Chiplet,Base Address,Chiplet Id - range,User,Register Name,Description/U ,XBUS,0x060F0042,0x06,HBFW,NET CTRL0 Register,Workaround to be removed by @TODO SW409746,write_whitelist, ,OBUS,0x09010805,0x09,HBFW,PowerBus OLL FIR Mask Register,Workaround to be removed by @TODO SW409746,write_whitelist, ,OBUS,0x0C010805,0x0C,HBFW,PowerBus OLL FIR Mask Register,Workaround to be removed by @TODO SW409746,write_whitelist, +,TP,0x0006C700,0x00,HB,AVSBus O2SCTRL First Frame Bus 0 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C701,0x00,HB,AVSBus O2SCTRL Second Frame Bus 0 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C702,0x00,HB,AVSBus O2SCTRL First Frame Bus 0 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C703,0x00,HB,AVSBus O2SCTRL1 Bus 0 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C707,0x00,HB,AVSBus O2SCMD Bus 0 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C708,0x00,HB,AVSBus O2SWD Bus 0 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C710,0x00,HB,AVSBus O2SCTRL First Frame Bus 0 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C711,0x00,HB,AVSBus O2SCTRL Second Frame Bus 0 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C712,0x00,HB,AVSBus O2SCTRL First Frame Bus 0 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C713,0x00,HB,AVSBus O2SCTRL1 Bus 0 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C717,0x00,HB,AVSBus O2SCMD Bus 0 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C718,0x00,HB,AVSBus O2SWD Bus 0 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C720,0x00,HB,AVSBus O2SCTRL First Frame Bus 1 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C721,0x00,HB,AVSBus O2SCTRL Second Frame Bus 1 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C722,0x00,HB,AVSBus O2SCTRL First Frame Bus 1 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C723,0x00,HB,AVSBus O2SCTRL1 Bus 1 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C727,0x00,HB,AVSBus O2SCMD Bus 1 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C728,0x00,HB,AVSBus O2SWD Bus 1 Bridge A,p9_setup_evid.C,write_whitelist, +,TP,0x0006C730,0x00,HB,AVSBus O2SCTRL First Frame Bus 1 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C731,0x00,HB,AVSBus O2SCTRL Second Frame Bus 1 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C732,0x00,HB,AVSBus O2SCTRL First Frame Bus 1 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C733,0x00,HB,AVSBus O2SCTRL1 Bus 1 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C737,0x00,HB,AVSBus O2SCMD Bus 1 Bridge B,p9_setup_evid.C,write_whitelist, +,TP,0x0006C738,0x00,HB,AVSBus O2SWD Bus 1 Bridge B,p9_setup_evid.C,write_whitelist, |
