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path: root/llvm/lib/Target/RISCV/RISCVISelLowering.h
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* CodeGen: Use LLT instead of EVT in getRegisterByNameMatt Arsenault2020-01-091-1/+1
* [RISCV] Implement the TargetLowering::getRegisterByName hookLuís Marques2019-11-041-0/+7
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-221-0/+6
* [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCallShiva Chen2019-08-281-0/+2
* [RISCV] Lower inline asm constraint A for RISC-VLewis Revill2019-08-161-0/+3
* [RISCV] Support 'f' Inline Assembly ConstraintSam Elliott2019-07-311-0/+1
* [RISCV] Specify registers used in DWARF exception handlingAlex Bradbury2019-07-081-0/+10
* [RISCV] Support @llvm.readcyclecounter() IntrinsicSam Elliott2019-07-051-1/+4
* [RISCV] Add lowering of global TLS addressesLewis Revill2019-06-191-0/+5
* [RISCV] Prevent re-ordering some adds after shiftsSam Elliott2019-06-181-0/+2
* [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splittingLuis Marques2019-06-171-0/+1
* [RISCV] Add lowering of addressing sequences for PICLewis Revill2019-06-111-1/+1
* [RISCV] Lower inline asm constraints I, J & K for RISC-VLewis Revill2019-06-111-0/+4
* [RISCV] Support Bit-Preserving FP in F/D ExtensionsSam Elliott2019-06-071-0/+2
* [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTSLuis Marques2019-04-161-0/+8
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-011-0/+4
* [RISCV] Allow conversion of CC logic to bitwise logicAlex Bradbury2019-03-221-0/+4
* [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64AAlex Bradbury2019-03-111-0/+4
* [RISCV][NFC] IsEligibleForTailCallOptimization -> isEligibleForTailCallOptimi...Alex Bradbury2019-02-211-3/+3
* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-311-1/+8
* [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64MAlex Bradbury2019-01-251-1/+6
* [RISCV] Custom-legalise 32-bit variable shifts on RV64Alex Bradbury2019-01-251-1/+13
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement fo...Alex Bradbury2018-11-301-0/+1
* [RISCV] Implement codegen for cmpxchg on RV32IAAlex Bradbury2018-11-291-0/+7
* [RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}Alex Bradbury2018-10-041-2/+2
* [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombineAlex Bradbury2018-10-031-0/+2
* [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32AAlex Bradbury2018-09-191-0/+9
* [RISCV] Remove unused functionRoger Ferrer Ibanez2018-08-171-1/+0
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-0/+3
* [RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury2018-06-131-0/+8
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-1/+6
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-261-0/+1
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-261-0/+2
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-261-0/+1
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-261-0/+1
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-261-0/+4
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-121-1/+3
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-201-0/+1
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-021-0/+3
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-101-0/+2
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-101-0/+4
* [RISCV] Support for varargsAlex Bradbury2018-01-101-1/+2
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-111-0/+10
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-0/+2
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-211-1/+7
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-1/+4
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-081-0/+1
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+62
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