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| author | Lewis Revill <lewis.revill@embecosm.com> | 2019-06-11 12:42:13 +0000 |
|---|---|---|
| committer | Lewis Revill <lewis.revill@embecosm.com> | 2019-06-11 12:42:13 +0000 |
| commit | 28a5cadb3ae0dfed9530dcbee8a0ec154f3f9f91 (patch) | |
| tree | 6d82f3352b8bef0dc1c59587be8b0274f84c9372 /llvm/lib/Target/RISCV/RISCVISelLowering.h | |
| parent | f63feaf3c2ff9a4360066a374d8345aa18169bca (diff) | |
| download | bcm5719-llvm-28a5cadb3ae0dfed9530dcbee8a0ec154f3f9f91.tar.gz bcm5719-llvm-28a5cadb3ae0dfed9530dcbee8a0ec154f3f9f91.zip | |
[RISCV] Lower inline asm constraints I, J & K for RISC-V
This validates and lowers arguments to inline asm nodes which have the
constraints I, J & K, with the following semantics (equivalent to GCC):
I: Any 12-bit signed immediate.
J: Immediate integer zero only.
K: Any 5-bit unsigned immediate.
Differential Revision: https://reviews.llvm.org/D54093
llvm-svn: 363054
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 8e756a1c522..f3bf4410686 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -93,6 +93,10 @@ public: getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override; + void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + std::vector<SDValue> &Ops, + SelectionDAG &DAG) const override; + MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; |
