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| author | Alex Bradbury <asb@lowrisc.org> | 2018-04-26 14:04:18 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-04-26 14:04:18 +0000 |
| commit | 15e894baeeb96612ae471fa83d1729a2d3388fc8 (patch) | |
| tree | 8f583b8c1ac66b8b2fa6966366b02f4f472c8654 /llvm/lib/Target/RISCV/RISCVISelLowering.h | |
| parent | e74f51924155bc6ee08ef527128dac9a645eccfd (diff) | |
| download | bcm5719-llvm-15e894baeeb96612ae471fa83d1729a2d3388fc8.tar.gz bcm5719-llvm-15e894baeeb96612ae471fa83d1729a2d3388fc8.zip | |
[RISCV] Implement isZextFree
This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected
and avoiding unnecessary masks.
llvm-svn: 330943
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 2a2016ef5f5..83a3bfdda4d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -46,6 +46,7 @@ public: bool isLegalAddImmediate(int64_t Imm) const override; bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; + bool isZExtFree(SDValue Val, EVT VT2) const override; // Provide custom lowering hooks for some operations. SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; |
