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| author | Shiva Chen <shiva0217@gmail.com> | 2018-02-02 02:43:18 +0000 |
|---|---|---|
| committer | Shiva Chen <shiva0217@gmail.com> | 2018-02-02 02:43:18 +0000 |
| commit | bbf4c5c25efafe9a52ea0ede070229e87034aae1 (patch) | |
| tree | 2512b413876f2f6e00afc5c2d308800f1a80f07f /llvm/lib/Target/RISCV/RISCVISelLowering.h | |
| parent | 74db26ff14589acceff47f1d277c6c82ef191dba (diff) | |
| download | bcm5719-llvm-bbf4c5c25efafe9a52ea0ede070229e87034aae1.tar.gz bcm5719-llvm-bbf4c5c25efafe9a52ea0ede070229e87034aae1.zip | |
[RISCV] Define getSetCCResultType for setting vector setCC type
To avoid trigger "No default SetCC type for vectors!" Assertion
Differential Revision: https://reviews.llvm.org/D42675
llvm-svn: 324054
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 8ee00cd69a1..6fbe2dd90f3 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -51,6 +51,9 @@ public: EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; + EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, + EVT VT) const override; + private: void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins, |
