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| author | Luis Marques <luismarques@lowrisc.org> | 2019-04-16 14:38:32 +0000 |
|---|---|---|
| committer | Luis Marques <luismarques@lowrisc.org> | 2019-04-16 14:38:32 +0000 |
| commit | 20d24240168295c3693e1b0d9b597a4b8f37b1b3 (patch) | |
| tree | 8d4b59f34e80aba8f29d137d375ab7ce2425f352 /llvm/lib/Target/RISCV/RISCVISelLowering.h | |
| parent | 4d88b17b3f282b1023400837c3249c9f27774eca (diff) | |
| download | bcm5719-llvm-20d24240168295c3693e1b0d9b597a4b8f37b1b3.tar.gz bcm5719-llvm-20d24240168295c3693e1b0d9b597a4b8f37b1b3.zip | |
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS
When not optimizing for minimum size (-Oz) we custom lower wide shifts
(SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall.
Differential Revision: https://reviews.llvm.org/D59477
llvm-svn: 358498
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 0686a7f4997..a7f397caaff 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -114,6 +114,12 @@ public: return ISD::SIGN_EXTEND; } + bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override { + if (DAG.getMachineFunction().getFunction().hasMinSize()) + return false; + return true; + } + private: void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -152,6 +158,8 @@ private: SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const; bool isEligibleForTailCallOptimization( CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, |
