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path: root/llvm/lib/Target/RISCV/RISCV.td
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxa...Shiva Chen2018-05-151-0/+4
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
* [RISCV] Pass MCSubtargetInfo to print methods.Ana Pazos2018-01-121-0/+5
* [RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury2017-12-121-0/+2
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-071-0/+7
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-071-0/+2
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+8
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+6
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-5/+12
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-091-4/+9
* [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0Alex Bradbury2017-11-081-3/+1
* [RISCV] Add missing hunk from r316188Alex Bradbury2017-10-191-1/+3
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-2/+5
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-191-5/+23
* [RISCV] Add basic RISCVAsmParserAlex Bradbury2017-08-081-0/+5
* [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.tdAlex Bradbury2016-11-011-0/+27
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