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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 12:50:32 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 12:50:32 +0000 |
| commit | 9f6aec4b7aab9a0c0d33bff634af0e148ed580ef (patch) | |
| tree | 3c927837c770161d62d555607491b2ba10679f83 /llvm/lib/Target/RISCV/RISCV.td | |
| parent | 87a54d611042449aff1c8f6ceee417af85dee193 (diff) | |
| download | bcm5719-llvm-9f6aec4b7aab9a0c0d33bff634af0e148ed580ef.tar.gz bcm5719-llvm-9f6aec4b7aab9a0c0d33bff634af0e148ed580ef.zip | |
[RISCV] MC layer support for load/store instructions of the C (compressed) extension
Differential Revision: https://reviews.llvm.org/D40001
Patch by Shiva Chen.
llvm-svn: 320037
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCV.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 88cf8c1831d..be339770ed1 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -38,6 +38,13 @@ def FeatureStdExtD def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, AssemblerPredicate<"FeatureStdExtD">; +def FeatureStdExtC + : SubtargetFeature<"c", "HasStdExtC", "true", + "'C' (Compressed Instructions)">; +def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, + AssemblerPredicate<"FeatureStdExtC">; + + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, |
