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path: root/llvm/lib/Target/RISCV/RISCV.td
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* [RISCV] Scheduler description for the Rocket coreKai Wang2020-02-031-0/+9
* [RISCV] Improve assembler missing feature warningsSimon Cook2019-12-101-8/+16
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-221-0/+5
* [RISCV] Add support for RVC HINT instructionsLuis Marques2019-08-211-2/+8
* [RISCV GlobalISel] Adding initial GlobalISel infrastructureDaniel Sanders2019-08-201-0/+1
* [RISCV][NFC] Replace hard-coded CSR duplication with symbolic referencesSam Elliott2019-07-051-6/+6
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-221-0/+6
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Support named operands for CSR instructions.Ana Pazos2018-10-041-0/+6
* [RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxa...Shiva Chen2018-05-151-0/+4
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
* [RISCV] Pass MCSubtargetInfo to print methods.Ana Pazos2018-01-121-0/+5
* [RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury2017-12-121-0/+2
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-071-0/+7
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-071-0/+2
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+8
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+6
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-5/+12
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-091-4/+9
* [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0Alex Bradbury2017-11-081-3/+1
* [RISCV] Add missing hunk from r316188Alex Bradbury2017-10-191-1/+3
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-2/+5
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-191-5/+23
* [RISCV] Add basic RISCVAsmParserAlex Bradbury2017-08-081-0/+5
* [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.tdAlex Bradbury2016-11-011-0/+27
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