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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:53:48 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:53:48 +0000 |
| commit | a6e6248307f716acde5239ff81d7ac053024936f (patch) | |
| tree | 57886e1b985270f184d1bf546bf0358b4471b140 /llvm/lib/Target/RISCV/RISCV.td | |
| parent | 7bc2a95bb98a5e589cf2a098f2b6c4eae3e4c072 (diff) | |
| download | bcm5719-llvm-a6e6248307f716acde5239ff81d7ac053024936f.tar.gz bcm5719-llvm-a6e6248307f716acde5239ff81d7ac053024936f.zip | |
[RISCV] MC layer support for the standard RV64I instructions
llvm-svn: 320024
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCV.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 3ebf76b8e59..88cf8c1831d 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -40,6 +40,8 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; +def IsRV64 : Predicate<"Subtarget->is64Bit()">, + AssemblerPredicate<"Feature64Bit">; def RV64 : HwMode<"+64bit">; def RV32 : HwMode<"-64bit">; |
