[RISCV] Prepare for the use of variable-sized register classes

While parameterising by XLen, also take the opportunity to clean up the 
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at 
<https://github.com/lowrisc/riscv-llvm>.

llvm-svn: 316159

1 files changed, 23 insertions, 5 deletions

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 19e11839ac3..7b61901915f 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -9,19 +9,37 @@
 
 include "llvm/Target/Target.td"
 
-include "RISCVRegisterInfo.td"
-include "RISCVInstrInfo.td"
+//===----------------------------------------------------------------------===//
+// RISC-V subtarget features and instruction predicates.
+//===----------------------------------------------------------------------===//
 
+def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
+                                    "Implements RV64">;
 
-def RISCVInstrInfo : InstrInfo;
+def RV64         : HwMode<"+64bit">;
+def RV32         : HwMode<"-64bit">;
+
+//===----------------------------------------------------------------------===//
+// Register file, instruction descriptions.
+//===----------------------------------------------------------------------===//
+
+include "RISCVRegisterInfo.td"
+include "RISCVInstrInfo.td"
 
-def Feature64Bit   : SubtargetFeature<"64bit", "HasRV64", "true",
-                                      "Implements RV64">;
+//===----------------------------------------------------------------------===//
+// RISC-V processors supported.
+//===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
+//===----------------------------------------------------------------------===//
+// Define the RISC-V target.
+//===----------------------------------------------------------------------===//
+
+def RISCVInstrInfo : InstrInfo;
+
 def RISCVAsmParser : AsmParser {
   let ShouldEmitMatchRegisterAltName = 1;
 }