[RISCV] MC layer support for the standard RV32A instruction set extension

llvm-svn: 317791

1 files changed, 12 insertions, 5 deletions

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index d8581f8d03c..63d2b827014 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -13,13 +13,20 @@ include "llvm/Target/Target.td"
 // RISC-V subtarget features and instruction predicates.
 //===----------------------------------------------------------------------===//
 
-def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true",
-                           "'M' (Integer Multiplication and Division)">;
-def HasStdExtM     : Predicate<"Subtarget->hasStdExtM()">,
+def FeatureStdExtM
+    : SubtargetFeature<"m", "HasStdExtM", "true",
+                       "'M' (Integer Multiplication and Division)">;
+def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
                            AssemblerPredicate<"FeatureStdExtM">;
 
-def Feature64Bit   : SubtargetFeature<"64bit", "HasRV64", "true",
-                           "Implements RV64">;
+def FeatureStdExtA
+    : SubtargetFeature<"a", "HasStdExtA", "true",
+                       "'A' (Atomic Instructions)">;
+def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
+                           AssemblerPredicate<"FeatureStdExtA">;
+
+def Feature64Bit
+    : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 
 def RV64           : HwMode<"+64bit">;
 def RV32           : HwMode<"-64bit">;