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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-12 15:46:15 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-12 15:46:15 +0000 |
| commit | 9ed84c8ae85a6274afc8c266dc662bd9e5a9fa21 (patch) | |
| tree | 699a549f9b59a4b242837a1b9d75d67db4c911c7 /llvm/lib/Target/RISCV/RISCV.td | |
| parent | 4c1394d67d77b63c73e3ebeae1f123e4ac35dbef (diff) | |
| download | bcm5719-llvm-9ed84c8ae85a6274afc8c266dc662bd9e5a9fa21.tar.gz bcm5719-llvm-9ed84c8ae85a6274afc8c266dc662bd9e5a9fa21.zip | |
[RISCV] Implement assembler pseudo instructions for RV32I and RV64I
Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.
Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.
Differential Revision: https://reviews.llvm.org/D40902
Patch by Mario Werner.
llvm-svn: 320487
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCV.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index be339770ed1..c74d560b2e0 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -49,6 +49,8 @@ def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate<"Feature64Bit">; +def IsRV32 : Predicate<"!Subtarget->is64Bit()">, + AssemblerPredicate<"!Feature64Bit">; def RV64 : HwMode<"+64bit">; def RV32 : HwMode<"-64bit">; |
