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path: root/llvm/lib/Target/R600/SIRegisterInfo.cpp
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* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-5/+5
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-191-0/+1
* R600/SI: Fix allocating flat_scr_lo / flat_scr_hiMatt Arsenault2014-11-251-0/+2
* R600/SI: Fix spilling of m0 registerTom Stellard2014-11-141-1/+9
* R600/SI: Make constant array staticMatt Arsenault2014-11-141-1/+1
* R600/SI: Add new helper isSGPRClassIDMatt Arsenault2014-09-241-7/+0
* R600/SI: Mark EXEC_LO and EXEC_HI as reservedTom Stellard2014-09-241-0/+6
* R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()Tom Stellard2014-09-241-1/+10
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-1/+114
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-3/+21
* R600/SI: Add enums for some hard-coded valuesTom Stellard2014-09-221-0/+8
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+23
* R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudosTom Stellard2014-08-211-9/+98
* R600/SI: Handle VCC in SIRegisterInfo::getPhysRegSubReg()Tom Stellard2014-08-211-0/+11
* R600: silence GCC warningSaleem Abdulrasool2014-07-211-0/+1
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-2/+46
* R600/SI: Add verifier check for immediates in register operands.Tom Stellard2014-07-021-0/+16
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-9/+0
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-5/+4
* Use range forMatt Arsenault2014-05-121-4/+3
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-0/+7
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
* R600/SI: Return the correct index for VGPRs in getHWRegIndex()Tom Stellard2014-03-311-1/+1
* Fix known typosAlp Toker2014-01-241-1/+1
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-0/+2
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-0/+8
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-6/+42
* Make method staticMatt Arsenault2013-11-101-1/+1
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
* R600/SI: Choose the correct MOV instruction for copying immediatesTom Stellard2013-08-141-0/+11
* R600/SI: Add more special cases for opcodes to ensureSRegLimit()Tom Stellard2013-08-061-0/+21
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-5/+3
* R600/SI: switch back to RegPressure schedulingChristian Konig2013-03-261-0/+5
* Add R600 backendTom Stellard2012-12-111-0/+48
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