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path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
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* eliminateFrameIndex() is even more complicated if frame ptr is used instead ↵Evan Cheng2007-02-071-20/+34
| | | | | | of SP when there are dynamic alloca's. llvm-svn: 33975
* Spill / restore should avoid modifying the condition register.Evan Cheng2007-02-071-34/+35
| | | | llvm-svn: 33971
* foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. ↵Evan Cheng2007-02-061-13/+19
| | | | | | tLDRspi / tSTRspi cannot target / store high registers. llvm-svn: 33958
* eliminateFrameIndex() bug when frame pointer is used as base register.Evan Cheng2007-02-061-23/+27
| | | | llvm-svn: 33945
* bugfix: SP isn't resetted when function has FP and there is no spills.Lauro Ramos Venancio2007-02-021-2/+3
| | | | llvm-svn: 33800
* Another thumb large stack offset codegen bug.Evan Cheng2007-02-021-5/+13
| | | | llvm-svn: 33795
* Ugh. Only meant to do this in thumb mode.Evan Cheng2007-02-021-5/+10
| | | | llvm-svn: 33780
* Also set alignment of stack-based structs to 4 in thumb mode.Evan Cheng2007-02-011-2/+1
| | | | llvm-svn: 33741
* Special epilogue for vararg functions. We cannot do a pop to pc becauseEvan Cheng2007-02-011-4/+20
| | | | | | | | | | | there follows a sp increment for the va register save region. Instead issue a separate pop to another register, increment sp, and then return: pop {r4, r5, r6, r7} pop {r3} add sp, #3 * 4 bx r3 llvm-svn: 33739
* Don't want to add FramePtr to callee save spill list twice.Evan Cheng2007-01-311-8/+2
| | | | llvm-svn: 33727
* Darwin ABI requires FP to point to stack slot of prev FP.Evan Cheng2007-01-311-3/+14
| | | | llvm-svn: 33724
* Update comment.Evan Cheng2007-01-311-1/+1
| | | | llvm-svn: 33721
* ARM fix: Miscompilation when frame pointer can't be eliminated. ↵Lauro Ramos Venancio2007-01-311-10/+9
| | | | | | Uninitialized frame pointer register is used. llvm-svn: 33703
* During PEI, if the immediate value of sp + offset is too large (i.e. somethingEvan Cheng2007-01-301-21/+102
| | | | | | | that would require > 3 instructions to materialize), load the immediate from a constpool entry. llvm-svn: 33667
* In thumb mode, round up stack frame size to multiple of 4 since add/subEvan Cheng2007-01-301-115/+124
| | | | | | sp, imm instructions implicitly multiply the offset by 4. llvm-svn: 33653
* Thumb eliminateFrameIndex fixes.Evan Cheng2007-01-301-8/+27
| | | | llvm-svn: 33652
* - In thumb mode, if size of MachineFunction is >= 2048, force LR to beEvan Cheng2007-01-301-3/+17
| | | | | | | | | | | | | spilled (if it is not already). - If LR is spilled, use BL to implement far jumps. LR is not used as a GPR in thumb mode so it can be clobbered if it is properly spilled / restored in prologue / epilogue. - If LR is force spilled but no far jump has been emitted, try undo'ing the spill by: push lr -> delete pop pc -> bx lr llvm-svn: 33650
* Remember if LR register has been spilled in this function.Evan Cheng2007-01-291-1/+5
| | | | llvm-svn: 33632
* Represent tADDspi and tSUBspi as two-address instructions.Evan Cheng2007-01-261-1/+1
| | | | llvm-svn: 33551
* I am an idiot.Evan Cheng2007-01-251-1/+1
| | | | llvm-svn: 33509
* PEI is now responsible for adding MaxCallFrameSize to frame size and align ↵Evan Cheng2007-01-231-15/+0
| | | | | | the stack. Each target can further adjust the frame size if necessary. llvm-svn: 33460
* hasFP() is now a virtual method of MRegisterInfo.Evan Cheng2007-01-231-1/+1
| | | | llvm-svn: 33455
* Round up stack to multiple of alignment only if it's a leaf function without ↵Evan Cheng2007-01-201-4/+7
| | | | | | alloca. llvm-svn: 33401
* Prologue and epilogue bugs for non-Darwin targets.Evan Cheng2007-01-201-22/+46
| | | | llvm-svn: 33390
* Clean up ARM PEI code.Evan Cheng2007-01-201-79/+65
| | | | llvm-svn: 33389
* isDarwin -> isTargetDarwinEvan Cheng2007-01-191-3/+3
| | | | llvm-svn: 33366
* ARM backend contribution from Apple.Evan Cheng2007-01-191-124/+904
| | | | llvm-svn: 33353
* Don't add or sub zero to sp.Lauro Ramos Venancio2007-01-121-6/+10
| | | | llvm-svn: 33142
* Build constants using instructions mov/orr or mvn/eor.Lauro Ramos Venancio2007-01-121-69/+6
| | | | llvm-svn: 33141
* Fix naming inconsistency.Evan Cheng2007-01-021-6/+6
| | | | llvm-svn: 32823
* macros -> Inline functionsRafael Espindola2006-12-181-9/+13
| | | | | | Lauros's patch llvm-svn: 32656
* Avoid creating invalid sub/add instructions on the prolog/epilogRafael Espindola2006-12-141-10/+86
| | | | | | patch by Lauro llvm-svn: 32577
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
| | | | llvm-svn: 32333
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-16/+18
| | | | | | of opcode and number of operands. llvm-svn: 31947
* implement load effective address similar to the alpha backendRafael Espindola2006-11-091-4/+4
| | | | | | remove lea_addri and the now unused memri addressing mode llvm-svn: 31592
* initial implementation of addressing mode 2Rafael Espindola2006-11-081-9/+9
| | | | | | TODO: fix lea_addri llvm-svn: 31552
* add support for calling functions when the caller has variable sized objectsRafael Espindola2006-10-311-1/+19
| | | | llvm-svn: 31312
* initial support for frame pointersRafael Espindola2006-10-261-4/+37
| | | | llvm-svn: 31197
* add the immediate to the Offset in eliminateFrameIndexRafael Espindola2006-10-171-2/+2
| | | | llvm-svn: 30998
* add FCPYS and FCPYDRafael Espindola2006-10-171-3/+11
| | | | llvm-svn: 30995
* fix the stack alignmentRafael Espindola2006-10-061-0/+3
| | | | llvm-svn: 30766
* add shifts to addressing mode 1Rafael Espindola2006-09-131-4/+8
| | | | llvm-svn: 30291
* partial implementation of the ARM Addressing Mode 1Rafael Espindola2006-09-111-4/+4
| | | | llvm-svn: 30252
* Completely eliminate def&use operands. Now a register operand is EITHER aChris Lattner2006-09-051-2/+2
| | | | | | def operand or a use operand. llvm-svn: 30109
* add a "load effective address"Rafael Espindola2006-08-171-1/+2
| | | | llvm-svn: 29748
* Declare the callee saved regsRafael Espindola2006-08-161-8/+10
| | | | | | | Remove the hard coded store and load of the link register Implement ARMFrameInfo llvm-svn: 29727
* correctly set LocalAreaOffset of TargetFrameInfoRafael Espindola2006-08-091-5/+0
| | | | llvm-svn: 29589
* fix the spill codeRafael Espindola2006-08-091-7/+9
| | | | llvm-svn: 29583
* fix the loading of the link register in emitepilogueRafael Espindola2006-08-091-1/+3
| | | | llvm-svn: 29580
* change the addressing mode of the str instruction to reg+immRafael Espindola2006-08-081-4/+2
| | | | llvm-svn: 29571
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