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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* [ARM] Fix null pointer dereference in CodeGen/ARM/Windows/stack-protector-msv...Fangrui Song2019-07-081-6/+8
* [ARM] Add support for MSVC stack cookie checkingMartin Storsjo2019-07-071-0/+30
* [ARM] MVE VMOV immediate handlingDavid Green2019-07-051-9/+18
* [ARM] MVE fp to int conversionsDavid Green2019-07-051-0/+7
* [ARM] Favour PL/MI over GE/LT when possibleDavid Green2019-07-041-0/+19
* [ARM] Fix for NDEBUG buildsSam Parker2019-07-031-4/+3
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-031-0/+9
* [ARM] MVE: allow soft-float ABI to pass vector types.Simon Tatham2019-07-021-2/+36
* [ARM] Stop using scalar FP instructions in integer-only MVE mode.Simon Tatham2019-07-021-16/+31
* [ARM] MVE: support QQPRRegClass and QQQQPRRegClassMikhail Maltsev2019-07-011-2/+3
* [ARM] WLS/LE Code GenerationSam Parker2019-07-011-0/+42
* [ARM] Add support for the MVE long shift instructionsSam Tebbs2019-06-281-2/+55
* [ARM] Mark math routines as non-legal for MVEDavid Green2019-06-281-0/+9
* [ARM] Widening loads and narrowing storesDavid Green2019-06-281-4/+21
* [ARM] MVE loads and storesDavid Green2019-06-281-11/+49
* [ARM] Mark div and rem as expand for MVEDavid Green2019-06-281-0/+12
* [ARM] MVE vector shufflesDavid Green2019-06-281-61/+128
* [ARM] Fix formatting issue in ARMISelLowering.cppSam Tebbs2019-06-271-1/+2
* [ARM] Don't reserve R12 on Thumb1 as an emergency spill slot.Eli Friedman2019-06-261-1/+2
* [ARM] Fix -Wimplicit-fallthrough after D60709/r364331Fangrui Song2019-06-261-4/+3
* [ARM] Support inline assembler constraints for MVE.Simon Tatham2019-06-251-1/+22
* [ARM] Code-generation infrastructure for MVE.Simon Tatham2019-06-251-5/+32
* [ARM] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D60692Fangrui Song2019-06-251-0/+1
* [ARM] Explicit lowering of half <-> double conversions.Simon Tatham2019-06-251-11/+68
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-4/+7
* [ARM] Adjust isLegalT1AddressImmediate for non-legal typesDavid Green2019-06-081-2/+2
* [ARM] Add MVE addressing to isLegalT2AddressImmediateDavid Green2019-06-081-1/+20
* [ARM] Add fp16 addressing to isLegalT2AddressImmediateDavid Green2019-06-081-0/+3
* [ARM][FIX] Ran out of registers due tail recursionDiogo N. Sampaio2019-06-031-40/+37
* [ARM] LowerVECTOR_SHUFFLE - fix uninitialized variable warnings. NFCI.Simon Pilgrim2019-05-301-4/+4
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-35/+35
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-1/+3
* [ARM] Select a number of fp16 rounding functionsDavid Green2019-05-261-0/+2
* [ARM] Promote various fp16 math intrinsicsDavid Green2019-05-261-0/+11
* [ARM] Promote fp16 fremDavid Green2019-05-261-0/+5
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-3/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-1/+3
* [ARM] Don't use the Machine Scheduler for cortex-m at minsizeDavid Green2019-05-151-1/+1
* [ARM] Glue register copies to tail calls.Eli Friedman2019-05-061-26/+4
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-301-8/+5
* [ARM] Rewrite isLegalT2AddressImmediateDavid Green2019-04-211-29/+24
* [TargetLowering] Rename preferShiftsToClearExtremeBits and shouldFoldShiftPai...Simon Pilgrim2019-04-161-3/+2
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-041-4/+4
* [ARM] Optimize expressions like "return x != 0;" for Thumb1.Eli Friedman2019-04-021-11/+13
* [ARM] Add missing memory operands to a bunch of instructions.Eli Friedman2019-03-251-3/+9
* [Thumb] Fix infinite loop in ABS expansion (PR41160)Simon Pilgrim2019-03-211-1/+4
* Fix unused variable warning. NFCI.Simon Pilgrim2019-03-191-2/+1
* [SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGB...Simon Pilgrim2019-03-191-0/+54
* [TargetLowering] Add code size information on isFPImmLegal. NFCAdhemerval Zanella2019-03-181-1/+2
* [ARM] Fixed an assumption of power-of-2 vector MVTTim Renouf2019-03-171-6/+6
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