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authorDavid Green <david.green@arm.com>2019-06-28 08:18:55 +0000
committerDavid Green <david.green@arm.com>2019-06-28 08:18:55 +0000
commitfc4102417b171357585d7fa786d0020bb60efab1 (patch)
tree6e5b396df84ec9966511e2af694c63292475819b /llvm/lib/Target/ARM/ARMISelLowering.cpp
parent8ab8a60a1ec899dbea8085599b9d018e128f3d18 (diff)
downloadbcm5719-llvm-fc4102417b171357585d7fa786d0020bb60efab1.tar.gz
bcm5719-llvm-fc4102417b171357585d7fa786d0020bb60efab1.zip
[ARM] Mark div and rem as expand for MVE
We don't have vector operations for these, so they need to be expanded for both integer and float. Differential Revision: https://reviews.llvm.org/D63595 llvm-svn: 364631
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index e7e652ddc9b..e4a47edc750 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -235,6 +235,12 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+
+ // No native support for these.
+ setOperationAction(ISD::UDIV, VT, Expand);
+ setOperationAction(ISD::SDIV, VT, Expand);
+ setOperationAction(ISD::UREM, VT, Expand);
+ setOperationAction(ISD::SREM, VT, Expand);
}
const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
@@ -252,6 +258,12 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
setOperationAction(ISD::BITCAST, VT, Legal);
setOperationAction(ISD::LOAD, VT, Legal);
setOperationAction(ISD::STORE, VT, Legal);
+
+ if (HasMVEFP) {
+ // No native support for these.
+ setOperationAction(ISD::FDIV, VT, Expand);
+ setOperationAction(ISD::FREM, VT, Expand);
+ }
}
// We 'support' these types up to bitcast/load/store level, regardless of
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