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| author | Sam Tebbs <sam.tebbs@arm.com> | 2019-06-27 16:28:28 +0000 |
|---|---|---|
| committer | Sam Tebbs <sam.tebbs@arm.com> | 2019-06-27 16:28:28 +0000 |
| commit | 8747c5f4828838cb08c4fb7c228169d5d9050308 (patch) | |
| tree | 2937b82367752f8613152a0771c5403768b447a2 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 41e20d21015bd3478ed57bd025c67e509469797b (diff) | |
| download | bcm5719-llvm-8747c5f4828838cb08c4fb7c228169d5d9050308.tar.gz bcm5719-llvm-8747c5f4828838cb08c4fb7c228169d5d9050308.zip | |
[ARM] Fix formatting issue in ARMISelLowering.cpp
Fix a formatting error in ARMISelLowering.cpp::Expand64BitShift. My test
commit after receiving write access.
llvm-svn: 364560
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 7ff0846e1a0..9785339ee7b 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5565,7 +5565,8 @@ static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, return SDValue(); // If we are in thumb mode, we don't have RRX. - if (ST->isThumb1Only()) return SDValue(); + if (ST->isThumb1Only()) + return SDValue(); // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), |
