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| author | Mikhail Maltsev <mikhail.maltsev@arm.com> | 2019-07-01 16:05:23 +0000 |
|---|---|---|
| committer | Mikhail Maltsev <mikhail.maltsev@arm.com> | 2019-07-01 16:05:23 +0000 |
| commit | 4a9e3f15bbb2c0259fd8e399a0323e275e4daff9 (patch) | |
| tree | ddf8fa32915e4b15cc8cf1a618f3783d39778d61 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 657f8c16c19e0df6234340f5755c8964268d06a4 (diff) | |
| download | bcm5719-llvm-4a9e3f15bbb2c0259fd8e399a0323e275e4daff9.tar.gz bcm5719-llvm-4a9e3f15bbb2c0259fd8e399a0323e275e4daff9.zip | |
[ARM] MVE: support QQPRRegClass and QQQQPRRegClass
Summary:
QQPRRegClass and QQQQPRRegClass are used by the
interleaving/deinterleaving loads/stores to represent sequences of
consecutive SIMD registers.
Reviewers: ostannard, simon_tatham, dmgreen
Reviewed By: simon_tatham
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64009
llvm-svn: 364794
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f2b6af1f1fd..632ee004c9f 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1565,8 +1565,9 @@ ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const { (void)isDivergent; // Map v4i64 to QQ registers but do not make the type legal. Similarly map // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to - // load / store 4 to 8 consecutive D registers. - if (Subtarget->hasNEON()) { + // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive + // MVE Q registers. + if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { if (VT == MVT::v4i64) return &ARM::QQPRRegClass; if (VT == MVT::v8i64) |
