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author | David Green <david.green@arm.com> | 2019-12-30 09:39:14 +0000 |
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committer | David Green <david.green@arm.com> | 2019-12-30 12:58:14 +0000 |
commit | b4abe7afbf5272d56ec8adb39fdccf1e2df48a88 (patch) | |
tree | f4c524edf018eca86011c20f25fe2aab8b692a7a /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
parent | a5a141544d0b3ce64c97ef9bb88ae5231e427b9f (diff) | |
download | bcm5719-llvm-b4abe7afbf5272d56ec8adb39fdccf1e2df48a88.tar.gz bcm5719-llvm-b4abe7afbf5272d56ec8adb39fdccf1e2df48a88.zip |
[ARM] Sink splat to ICmp
This adds ICmp to the list of instructions that we sink a splat to in a
loop, allowing the register forms of instructions to be selected more
often. It does not add FCmp yet as the results look a little odd, trying
to keep the register in an float reg and having to move it back to a GPR.
Differential Revision: https://reviews.llvm.org/D70997
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index bfc78a95e55..3e27a1b8343 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -14913,6 +14913,7 @@ bool ARMTargetLowering::shouldSinkOperands(Instruction *I, switch (I->getOpcode()) { case Instruction::Add: case Instruction::Mul: + case Instruction::ICmp: return true; case Instruction::Sub: case Instruction::Shl: |