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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-12-28 09:18:56 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-09 17:37:52 -0500 |
| commit | 255cc5a7603fef251192daab2a3336acbcd9aa1c (patch) | |
| tree | 2cf2ad36b609f4095c43712a5e629051f8907ee2 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | cc95bb1f57c674c0efdfc134eab8ed8c50f2a6e3 (diff) | |
| download | bcm5719-llvm-255cc5a7603fef251192daab2a3336acbcd9aa1c.tar.gz bcm5719-llvm-255cc5a7603fef251192daab2a3336acbcd9aa1c.zip | |
CodeGen: Use LLT instead of EVT in getRegisterByName
Only PPC seems to be using it, and only checks some simple cases and
doesn't distinguish between FP. Just switch to using LLT to simplify
use from GlobalISel.
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0e1f1c37fb6..00a1a45b4ef 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5614,7 +5614,7 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT, +Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const { Register Reg = StringSwitch<unsigned>(RegName) .Case("sp", ARM::SP) |
