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| author | David Green <david.green@arm.com> | 2020-04-26 21:58:58 +0100 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2020-05-19 12:11:06 -0700 |
| commit | f3164f752708753323e2e6a8d17e703cfeb69be6 (patch) | |
| tree | c2d734193f5534e31d734b706254e382eb26dedd /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 3de89abf189e63da4edbfda509ed3d421bdba1a9 (diff) | |
| download | bcm5719-llvm-f3164f752708753323e2e6a8d17e703cfeb69be6.tar.gz bcm5719-llvm-f3164f752708753323e2e6a8d17e703cfeb69be6.zip | |
[ARM] Only produce qadd8b under hasV6Ops
When compiling for a arm5te cpu from clang, the +dsp attribute is set.
This meant we could try and generate qadd8 instructions where we would
end up having no pattern. I've changed the condition here to be hasV6Ops
&& hasDSP, which is what other parts of ARMISelLowering seem to use for
similar instructions.
Fixed PR45677.
Differential Revision: https://reviews.llvm.org/D78877
(cherry picked from commit 8807139026b64ac40163bb255dad38a1d8054f08)
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 66f3f418d06..9f504b1eaa4 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4549,7 +4549,7 @@ SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op, static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) { EVT VT = Op.getValueType(); - if (!Subtarget->hasDSP()) + if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) return SDValue(); if (!VT.isSimple()) return SDValue(); |
