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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* TLI: Remove DAG argument from getRegisterByNameMatt Arsenault2019-10-011-3/+3
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-5/+3
* [ARM] Ensure we do not attempt to create lsll #0David Green2019-09-251-1/+1
* [ARM] Split large widening MVE loadsDavid Green2019-09-241-3/+72
* [ARM] Split large truncating MVE storesDavid Green2019-09-241-82/+148
* [Alignment] Get DataLayout::StackAlignment as AlignGuillaume Chatelet2019-09-231-1/+2
* [ARM] Fix CTTZ not generating correct instructions MVEOliver Cruickshank2019-09-201-1/+1
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-12/+12
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-12/+12
* [ARM] MVE i1 splatDavid Green2019-09-191-1/+13
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-12/+12
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-4/+4
* [ARM] A predicate cast of a predicate cast is a predicate castDavid Green2019-09-161-0/+20
* [ARM] Add patterns for BSWAP intrinsic on MVEOliver Cruickshank2019-09-161-0/+1
* [ARM] Add patterns for bitreverse intrinsic on MVEOliver Cruickshank2019-09-161-0/+1
* [ARM] Lower CTTZ on MVEOliver Cruickshank2019-09-161-2/+2
* [ARM] Add patterns for CTLZ on MVEOliver Cruickshank2019-09-161-0/+1
* [ARM] Masked loads and storesDavid Green2019-09-151-0/+31
* [ARM] Add support for MVE vmaxv and vminvSam Tebbs2019-09-131-0/+4
* [Alignment] Use Align for TargetLowering::MinStackArgumentAlignmentGuillaume Chatelet2019-09-101-1/+1
* [ARM] Fix loads and stores for predicate vectorsDavid Green2019-09-091-0/+65
* Fix MSVC "32-bit shift implicitly converted to 64 bits" warnings. NFCI.Simon Pilgrim2019-09-071-1/+1
* [ARM] Sink add/mul(shufflevector(insertelement())) for MVE instruction selectionSam Tebbs2019-09-061-10/+48
* [Alignment][NFC] Use Align with TargetLowering::setPrefLoopAlignmentGuillaume Chatelet2019-09-061-1/+2
* [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignmentGuillaume Chatelet2019-09-061-1/+2
* [ARM] Add support for the s,j,x,N,O inline asm constraintsDavid Candler2019-09-051-3/+3
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-2/+2
* [ARM] Invert CSEL predicates if the opposite is a simpler constant to materia...David Green2019-09-031-0/+9
* [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.David Green2019-09-031-0/+46
* [ARM] Use MQPR not QPR for MVE registersDavid Green2019-09-021-3/+3
* [ARM] Remove MVE masked loads/storesDavid Green2019-09-011-31/+0
* [ARM] MVE Masked loads and storesDavid Green2019-08-291-0/+31
* [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCallShiva Chen2019-08-281-2/+2
* [TargetLowering] Add buildLegalVectorShuffle facility to help build legal shu...Amaury Sechet2019-08-281-5/+4
* Reapply: [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32Sam Tebbs2019-08-221-6/+7
* Revert r369626 "[ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32"Hans Wennborg2019-08-221-7/+6
* [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32Sam Tebbs2019-08-221-6/+7
* [TargetLowering] Remove optional arguments passing to makeLibCallShiva Chen2019-08-221-5/+9
* [ARM] Add support for MVE vaddvSam Tebbs2019-08-191-0/+3
* Reland "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-0/+44
* Revert "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-44/+0
* [ARM] push LR before __gnu_mcount_ncJian Cai2019-08-161-0/+44
* [ARM] Don't pretend we know how to generate MVE VLDnDavid Green2019-08-161-0/+6
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-57/+57
* [ARM] Add support for MVE pre and post inc loads and storesDavid Green2019-08-081-15/+106
* [ARM] MVE big endian loads/storesDavid Green2019-08-081-36/+12
* [ARM] Tighten up VLDRH.32 with low alignmentsDavid Green2019-08-081-3/+10
* [ARM] Expand CTPOP intrinsic for MVEOliver Cruickshank2019-08-071-0/+1
* AMDGPU: Correct behavior of f16 buffer loadsMatt Arsenault2019-08-051-2/+3
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-8/+8
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