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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* [AMDGPU] Widened vector length for global/constant address space.Farhana Aleen2018-03-071-2/+8
* [TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombi...Craig Topper2018-03-061-1/+1
* Pass Divergence Analysis data to Selection DAG to drive divergenceAlexander Timofeev2018-03-051-2/+2
* AMDGPU/GCN: Promote i16 ctpopJan Vesely2018-03-021-0/+1
* AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instru...Changpeng Fang2018-02-161-38/+23
* [AMDGPU] Remove non-temporal flag from argument loadsStanislav Mekhanoshin2018-02-141-1/+0
* Reapply "AMDGPU: Add 32-bit constant address space"Matt Arsenault2018-02-091-9/+21
* AMDGPU: Fix layering issueMatt Arsenault2018-02-091-1/+1
* Revert "AMDGPU: Add 32-bit constant address space"Rafael Espindola2018-02-071-21/+9
* AMDGPU: Add 32-bit constant address spaceMarek Olsak2018-02-071-9/+21
* AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}Marek Olsak2018-01-311-4/+46
* [AMDGPU] fix LDS f32 intrinsicsDaniil Fukalov2018-01-261-12/+12
* AMDGPU/SI: Add d16 support for image intrinsics.Changpeng Fang2018-01-181-24/+320
* [AMDGPU] add LDS f32 intrinsicsDaniil Fukalov2018-01-171-6/+36
* AMDGPU/SI: Add d16 support for buffer intrinsics.Changpeng Fang2018-01-121-20/+131
* AMDGPU: Use unique PSVs for buffer resourcesMatt Arsenault2017-12-291-32/+78
* AMDGPU: Implement getTgtMemIntrinsic for imagesMatt Arsenault2017-12-291-15/+154
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-15/+15
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-141-0/+1
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-141-3/+4
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-131-1/+2
* AMDGPU: image_getlod and image_getresinfo do not read memoryMatt Arsenault2017-12-081-13/+32
* AMDGPU: Preserve MMO in adjustWritemaskMatt Arsenault2017-12-081-0/+2
* AMDGPU: Fix creating invalid copy when adjusting dmaskMatt Arsenault2017-12-041-46/+42
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-0/+8
* DAG: Add nuw when splitting loads and storesMatt Arsenault2017-11-291-6/+5
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-1/+1
* [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argumentYaxun Liu2017-11-221-2/+3
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-151-4/+48
* AMDGPU: Don't use MUBUF vaddr if address may overflowMatt Arsenault2017-11-151-1/+35
* AMDGPU: Handle or in multi-use shl ptr combineMatt Arsenault2017-11-141-2/+2
* AMDGPU: Preserve nuw in shl add ptr combineMatt Arsenault2017-11-131-1/+6
* AMDGPU: Fix multi-use shl/add combineMatt Arsenault2017-11-131-31/+14
* AMDGPU: Lower buffer store and atomic intrinsics manuallyMarek Olsak2017-11-091-0/+113
* AMDGPU: Select v_mad_u64_u32 and v_mad_i64_i32Matt Arsenault2017-11-061-4/+43
* [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bitYaxun Liu2017-11-061-5/+10
* AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1)Marek Olsak2017-10-241-3/+4
* Use the return value of UpdateNodeOperands(); in some cases, UpdateNodeOperan...Mark Searles2017-10-161-2/+1
* AMDGPU: Implement hasBitPreservingFPLogicMatt Arsenault2017-10-131-0/+4
* [AMDGPU] For amdpal, widen interpolation mode workaroundTim Renouf2017-10-121-8/+25
* AMDGPU: Set v2i32 any_extend to expandMatt Arsenault2017-10-051-0/+1
* AMDGPU: VALU carry-in and v_cndmask condition cannot be EXECNicolai Haehnle2017-09-291-2/+5
* AMDGPU: Start selecting v_mad_mixhi_f16Matt Arsenault2017-09-201-1/+45
* AMDGPU: Stop modifying SP in call sequencesMatt Arsenault2017-09-141-3/+3
* AMDGPU: Make frame register caller preservedMatt Arsenault2017-09-141-0/+15
* AMDGPU: Don't legalize i16 extloads to i32 with legal i16Matt Arsenault2017-09-071-0/+3
* AMDGPU: Select clamp pattern with v2f16Matt Arsenault2017-08-301-15/+30
* AMDGPU: Start adding tail call supportMatt Arsenault2017-08-111-19/+185
* [AMDGPU] Add support for Whole Wavefront ModeConnor Abbott2017-08-041-0/+5
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