| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | [AMDGPU] Add an llvm.amdgcn.wqm intrinsic for WQM | Connor Abbott | 2017-08-04 | 1 | -0/+5 |
| * | AMDGPU: Remove pointless asserts | Matt Arsenault | 2017-08-04 | 1 | -3/+0 |
| * | AMDGPU: Don't use report_fatal_error for unsupported call types | Matt Arsenault | 2017-08-03 | 1 | -6/+16 |
| * | AMDGPU: Remove error on calls for amdgcn | Matt Arsenault | 2017-08-03 | 1 | -5/+0 |
| * | AMDGPU: Fix implicitarg.ptr handling special inputs | Matt Arsenault | 2017-08-03 | 1 | -3/+18 |
| * | AMDGPU: Pass special input registers to functions | Matt Arsenault | 2017-08-03 | 1 | -45/+250 |
| * | AMDGPU: Analyze callee resource usage in AsmPrinter | Matt Arsenault | 2017-08-02 | 1 | -3/+16 |
| * | AMDGPU: Don't place arguments in emergency stack slot | Matt Arsenault | 2017-08-02 | 1 | -1/+9 |
| * | AMDGPU: Fix handling of div_scale with undef inputs | Matt Arsenault | 2017-08-01 | 1 | -1/+55 |
| * | AMDGPU: Initial implementation of calls | Matt Arsenault | 2017-08-01 | 1 | -7/+399 |
| * | AMDGPU: Teach isLegalAddressingMode about global_* instructions | Matt Arsenault | 2017-07-29 | 1 | -16/+24 |
| * | AMDGPU: Annotate implicitarg.ptr usage | Matt Arsenault | 2017-07-28 | 1 | -2/+10 |
| * | TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<in... | Zvi Rackover | 2017-07-26 | 1 | -2/+1 |
| * | [SystemZ, LoopStrengthReduce] | Jonas Paulsson | 2017-07-21 | 1 | -1/+1 |
| * | AMDGPU: Figure out private memory regs after lowering | Matt Arsenault | 2017-07-18 | 1 | -23/+42 |
| * | AMDGPU: Return correct type during argument lowering | Matt Arsenault | 2017-07-15 | 1 | -0/+27 |
| * | [AMDGPU] fcaninicalize optimization for GFX9+ | Stanislav Mekhanoshin | 2017-07-13 | 1 | -8/+19 |
| * | [AMDGPU] fcanonicalize elimination optimization | Stanislav Mekhanoshin | 2017-07-12 | 1 | -9/+86 |
| * | Add DAG argument to canMergeStoresTo NFC. | Nirav Dave | 2017-07-10 | 1 | -1/+2 |
| * | [AMDGPU] Fix -Wimplicit-fallthrough warning. NFCI. | Simon Pilgrim | 2017-07-08 | 1 | -6/+2 |
| * | [AMDGPU] Always use rcp + mul with fast math | Stanislav Mekhanoshin | 2017-07-06 | 1 | -7/+5 |
| * | [Constants] If we already have a ConstantInt*, prefer to use isZero/isOne/isM... | Craig Topper | 2017-07-06 | 1 | -1/+1 |
| * | [AMDGPU] Simplify setcc (sext from i1 b), -1|0, cc | Stanislav Mekhanoshin | 2017-06-27 | 1 | -1/+29 |
| * | [AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0 | Stanislav Mekhanoshin | 2017-06-27 | 1 | -2/+28 |
| * | AMDGPU: Whitespace fixes | Matt Arsenault | 2017-06-26 | 1 | -1/+1 |
| * | AMDGPU: Partially fix implicit.buffer.ptr intrinsic handling | Matt Arsenault | 2017-06-26 | 1 | -5/+9 |
| * | [AMDGPU] Add intrinsics for tbuffer load and store - build error fix | David Stuttard | 2017-06-22 | 1 | -2/+1 |
| * | [AMDGPU] Add intrinsics for tbuffer load and store | David Stuttard | 2017-06-22 | 1 | -30/+96 |
| * | [AMDGPU] Add FP_CLASS to the add/setcc combine | Stanislav Mekhanoshin | 2017-06-21 | 1 | -1/+3 |
| * | [AMDGPU] Combine add and adde, sub and sube | Stanislav Mekhanoshin | 2017-06-21 | 1 | -9/+79 |
| * | [AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setcc | Stanislav Mekhanoshin | 2017-06-21 | 1 | -0/+39 |
| * | AMDGPU: Cleanup CreateLiveInRegister | Matt Arsenault | 2017-06-19 | 1 | -9/+0 |
| * | AMDGPU: Teach isLegalAddressingMode about flat offsets | Matt Arsenault | 2017-06-12 | 1 | -3/+11 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -2/+2 |
| * | [llvm] Remove double semicolons | Mandeep Singh Grang | 2017-06-06 | 1 | -1/+1 |
| * | AMDGPUAnnotateUniformValue should always treat volatile loads as divergent | Alexander Timofeev | 2017-06-02 | 1 | -1/+1 |
| * | [AMDGPU] Prevent too large store merges in AMDGPU Subtargets. NFCI. | Nirav Dave | 2017-05-24 | 1 | -0/+12 |
| * | [AMDGPU] Combine and (srl) into shl (bfe) | Stanislav Mekhanoshin | 2017-05-23 | 1 | -6/+34 |
| * | AMDGPU: Start defining a calling convention | Matt Arsenault | 2017-05-17 | 1 | -15/+150 |
| * | AMDGPU: Make better use of op_sel with high components | Matt Arsenault | 2017-05-17 | 1 | -0/+9 |
| * | AMDGPU: Fix min3/max3 combines for f16/i16 | Matt Arsenault | 2017-05-17 | 1 | -1/+2 |
| * | [AMDGPU] Placate unused variable warning in release builds. | Davide Italiano | 2017-05-11 | 1 | -0/+1 |
| * | AMDGPU: Pull fneg out of extract_vector_elt | Matt Arsenault | 2017-05-11 | 1 | -0/+21 |
| * | AMDGPU: GFX9 GS and HS shaders always have the scratch wave offset in SGPR5 | Marek Olsak | 2017-05-04 | 1 | -3/+11 |
| * | Generalize the specialized flag-carrying SDNodes by moving flags into SDNode. | Amara Emerson | 2017-05-01 | 1 | -9/+8 |
| * | AMDGPU: Add new amdgcn.init.exec intrinsics | Marek Olsak | 2017-04-28 | 1 | -0/+65 |
| * | [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDem... | Craig Topper | 2017-04-28 | 1 | -2/+3 |
| * | Move size and alignment information of regclass to TargetRegisterInfo | Krzysztof Parzyszek | 2017-04-24 | 1 | -10/+11 |
| * | AMDGPU: Move trap lowering to DAG | Matt Arsenault | 2017-04-24 | 1 | -46/+57 |
| * | AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormals | Konstantin Zhuravlyov | 2017-04-21 | 1 | -2/+4 |
