diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-12-14 22:34:10 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-12-14 22:34:10 +0000 |
| commit | 7d7adf4f2e4e50f738a5f692e6f011dcfca6b070 (patch) | |
| tree | df846d9653c67e5bcd684da57d8dc97665c057b3 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | c7bc461298d540cefec9ffe370f68dfbca367e8b (diff) | |
| download | bcm5719-llvm-7d7adf4f2e4e50f738a5f692e6f011dcfca6b070.tar.gz bcm5719-llvm-7d7adf4f2e4e50f738a5f692e6f011dcfca6b070.zip | |
TLI: Allow using PSV for intrinsic mem operands
llvm-svn: 320756
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index dd5e964fa42..d3e2e11b721 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -558,6 +558,7 @@ bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const { bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &CI, + MachineFunction &MF, unsigned IntrID) const { switch (IntrID) { case Intrinsic::amdgcn_atomic_inc: |
