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| author | Daniil Fukalov <daniil.fukalov@amd.com> | 2018-01-26 11:09:38 +0000 |
|---|---|---|
| committer | Daniil Fukalov <daniil.fukalov@amd.com> | 2018-01-26 11:09:38 +0000 |
| commit | 6e1dc6811773c76b337fd2ff924b407eb42605bc (patch) | |
| tree | d087ba04d8fde36dec4aef3968472e8f6f1afc67 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | 212afb9fd9c24e9f2e32d77deb7c456bee49193f (diff) | |
| download | bcm5719-llvm-6e1dc6811773c76b337fd2ff924b407eb42605bc.tar.gz bcm5719-llvm-6e1dc6811773c76b337fd2ff924b407eb42605bc.zip | |
[AMDGPU] fix LDS f32 intrinsics
- using qualified pointer addrspace in intrinsics class to avoid .f32 mangling
- changed too common atomic mangling to ds
- added missing intrinsics to AMDGPUTTIImpl::getTgtMemIntrinsic
Reviewed by: b-sumner
Differential Revision: https://reviews.llvm.org/D42383
llvm-svn: 323516
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 7dc9dcf31fc..913bf078679 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -566,9 +566,9 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, switch (IntrID) { case Intrinsic::amdgcn_atomic_inc: case Intrinsic::amdgcn_atomic_dec: - case Intrinsic::amdgcn_atomic_fadd: - case Intrinsic::amdgcn_atomic_fmin: - case Intrinsic::amdgcn_atomic_fmax: { + case Intrinsic::amdgcn_ds_fadd: + case Intrinsic::amdgcn_ds_fmin: + case Intrinsic::amdgcn_ds_fmax: { Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::getVT(CI.getType()); Info.ptrVal = CI.getOperand(0); @@ -807,9 +807,9 @@ bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II, switch (II->getIntrinsicID()) { case Intrinsic::amdgcn_atomic_inc: case Intrinsic::amdgcn_atomic_dec: - case Intrinsic::amdgcn_atomic_fadd: - case Intrinsic::amdgcn_atomic_fmin: - case Intrinsic::amdgcn_atomic_fmax: { + case Intrinsic::amdgcn_ds_fadd: + case Intrinsic::amdgcn_ds_fmin: + case Intrinsic::amdgcn_ds_fmax: { Value *Ptr = II->getArgOperand(0); AccessTy = II->getType(); Ops.push_back(Ptr); @@ -4827,9 +4827,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, switch (IntrID) { case Intrinsic::amdgcn_atomic_inc: case Intrinsic::amdgcn_atomic_dec: - case Intrinsic::amdgcn_atomic_fadd: - case Intrinsic::amdgcn_atomic_fmin: - case Intrinsic::amdgcn_atomic_fmax: { + case Intrinsic::amdgcn_ds_fadd: + case Intrinsic::amdgcn_ds_fmin: + case Intrinsic::amdgcn_ds_fmax: { MemSDNode *M = cast<MemSDNode>(Op); unsigned Opc; switch (IntrID) { @@ -4839,13 +4839,13 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, case Intrinsic::amdgcn_atomic_dec: Opc = AMDGPUISD::ATOMIC_DEC; break; - case Intrinsic::amdgcn_atomic_fadd: + case Intrinsic::amdgcn_ds_fadd: Opc = AMDGPUISD::ATOMIC_LOAD_FADD; break; - case Intrinsic::amdgcn_atomic_fmin: + case Intrinsic::amdgcn_ds_fmin: Opc = AMDGPUISD::ATOMIC_LOAD_FMIN; break; - case Intrinsic::amdgcn_atomic_fmax: + case Intrinsic::amdgcn_ds_fmax: Opc = AMDGPUISD::ATOMIC_LOAD_FMAX; break; default: |
