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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-13 05:33:35 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-13 05:33:35 +0000 |
| commit | e5e0c742df5e6a54154112d17ae888b662926fea (patch) | |
| tree | 1a5d3f927486e2914f429d4092d44334dd40d324 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | d4f6094091de107f9ce11d814d8e519f8cf8ac55 (diff) | |
| download | bcm5719-llvm-e5e0c742df5e6a54154112d17ae888b662926fea.tar.gz bcm5719-llvm-e5e0c742df5e6a54154112d17ae888b662926fea.zip | |
AMDGPU: Preserve nuw in shl add ptr combine
llvm-svn: 318017
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 73cd6971660..0be8e810545 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5229,7 +5229,12 @@ SDValue SITargetLowering::performSHLPtrCombine(SDNode *N, SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1); SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32); - return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset); + SDNodeFlags Flags; + Flags.setNoUnsignedWrap(N->getFlags().hasNoUnsignedWrap() && + (N0.getOpcode() == ISD::OR || + N0->getFlags().hasNoUnsignedWrap())); + + return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset, Flags); } SDValue SITargetLowering::performMemSDNodeCombine(MemSDNode *N, |
