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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-13 21:10:22 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-10-13 21:10:22 +0000 |
| commit | e11d8aca77dcdd17a8a25bdf84f0e13d57e53d41 (patch) | |
| tree | 84ac8959676371349d6635df3c0b2dbafb839d37 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | 868783e85557dde30923fab94c7ffabf5e271818 (diff) | |
| download | bcm5719-llvm-e11d8aca77dcdd17a8a25bdf84f0e13d57e53d41.tar.gz bcm5719-llvm-e11d8aca77dcdd17a8a25bdf84f0e13d57e53d41.zip | |
AMDGPU: Implement hasBitPreservingFPLogic
llvm-svn: 315754
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 2bc3d7fa508..82d1bc270a4 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3107,6 +3107,10 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( } } +bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const { + return isTypeLegal(VT.getScalarType()); +} + bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const { // This currently forces unfolding various combinations of fsub into fma with // free fneg'd operands. As long as we have fast FMA (controlled by |
