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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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* [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a poin...Craig Topper2016-07-011-3/+2
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP and...Simon Pilgrim2016-05-121-5/+32
* [SelectionDAG] BITREVERSE vector legalization of bit operations (REAPPLIED)Simon Pilgrim2016-05-041-2/+2
* Revert r268504Simon Pilgrim2016-05-041-2/+2
* [SelectionDAG] BITREVERSE vector legalization of bit operationsSimon Pilgrim2016-05-041-2/+2
* [SelectionDAG] Teach LegalizeVectorOps to directly Expand CTTZ_ZERO_UNDEF/CTL...Craig Topper2016-04-211-3/+5
* LegalizeDAG: Don't replace vector store with integer if not legalMatt Arsenault2016-03-301-41/+27
* LegalizeDAG: Don't replace vector load with integer unless legalMatt Arsenault2016-03-301-28/+21
* [X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_...Simon Pilgrim2016-03-101-1/+1
* [CodeGen] Document and use getConstant's splat-building feature. NFC.Ahmed Bougacha2016-02-151-4/+1
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-091-2/+1
* [SelectionDAG] Teach LegalizeVectorOps to not unroll CTLZ_ZERO_UNDEF and CTTZ...Craig Topper2015-12-271-0/+14
* AMDGPU: Use generic bitreverse intrinsicMatt Arsenault2015-12-141-1/+24
* Revert r248483, r242546, r242545, and r242409 - absdiff intrinsicsHal Finkel2015-12-111-34/+0
* AVX-512: Fixed masked load / store instruction selection for KNL.Elena Demikhovsky2015-12-071-1/+4
* Fix some places where we were assuming that memory type had been legalizedEric Christopher2015-11-251-1/+1
* Do not use "else" when both branches return (NFC)Mehdi Amini2015-10-271-2/+1
* Two switch blocks in VectorLegalizer::LegalizeOp already have aArtyom Skrobov2015-10-201-0/+1
* Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into DA...Artyom Skrobov2015-10-201-0/+2
* SelectionDAG: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-131-1/+1
* Codegen: Fix llvm.*absdiff semantic.Mohammad Shahid2015-09-241-16/+22
* propagate fast-math-flags on DAG nodesSanjay Patel2015-09-161-2/+4
* Add new ISD nodes: ISD::FMINNAN and ISD::FMAXNANJames Molloy2015-08-111-0/+2
* [Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute dif...James Molloy2015-07-161-0/+28
* Make TargetLowering::getShiftAmountTy() taking DataLayout as an argumentMehdi Amini2015-07-091-5/+8
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-8/+12
* Redirect DataLayout from TargetMachine to Module in SelectionDAGMehdi Amini2015-07-071-2/+2
* Convert a bunch of loops to foreach. NFC.Pete Cooper2015-06-261-2/+2
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
* Add SDNodes for umin, umax, smin and smax.James Molloy2015-05-151-0/+4
* Masked gather and scatter intrinsics - enabled codegen for KNL.Elena Demikhovsky2015-05-031-2/+6
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-25/+28
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-28/+25
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-25/+28
* fix typo and 80-col; NFCSanjay Patel2015-03-271-2/+2
* [SDAG] Handle LowerOperation returning its input consistentlyHal Finkel2015-02-241-3/+7
* [SDAG] Use correct alignments on expanded vector trunc-store/ext-loadsHal Finkel2015-02-221-4/+7
* [SDAG] Don't try to use FP_EXTEND/FP_ROUND for int<->fp promotionsHal Finkel2015-02-121-3/+5
* Fixes a bug in vector load legalization that confused bits and bytes.Michael Kuperstein2015-02-041-3/+3
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-1/+2
* Add minnum / maxnum codegenMatt Arsenault2014-10-211-0/+2
* Teach the AArch64 backend about v4f16 and v8f16Oliver Stannard2014-08-271-6/+17
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-311-3/+3
* [x86] Make vector legalization of extloads work more like the "normal"Chandler Carruth2014-07-241-5/+22
* AA metadata refactoring (introduce AAMDNodes)Hal Finkel2014-07-241-5/+5
* [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogousChandler Carruth2014-07-101-0/+66
* Make it possible for ints/floats to return different values from getBooleanCo...Daniel Sanders2014-07-101-3/+3
* [x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when wideningChandler Carruth2014-07-091-0/+42
* [cleanup] Hoist an if-else chain on ISD opcodes (really designed forChandler Carruth2014-07-021-17/+28
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