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| author | Sanjay Patel <spatel@rotateright.com> | 2015-03-27 21:45:18 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-03-27 21:45:18 +0000 |
| commit | f176566a00f02502a88764eab0a3259ed12fc815 (patch) | |
| tree | 34dd71fbe43d80e3ff82f45c1c9212e2a8ad224c /llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | |
| parent | f089372c5cff0ff37931e5f1b2cb20bbebf15ae1 (diff) | |
| download | bcm5719-llvm-f176566a00f02502a88764eab0a3259ed12fc815.tar.gz bcm5719-llvm-f176566a00f02502a88764eab0a3259ed12fc815.zip | |
fix typo and 80-col; NFC
llvm-svn: 233427
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 03c2734a9e4..408d5eda4e7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -379,8 +379,8 @@ SDValue VectorLegalizer::Promote(SDValue Op) { // There are currently two cases of vector promotion: // 1) Bitcasting a vector of integers to a different type to a vector of the - // same overall length. For example, x86 promotes ISD::AND on v2i32 to v1i64. - // 2) Extending a vector of floats to a vector of the same number oflarger + // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64. + // 2) Extending a vector of floats to a vector of the same number of larger // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32. MVT VT = Op.getSimpleValueType(); assert(Op.getNode()->getNumValues() == 1 && |
