diff options
| author | Guillaume Chatelet <gchatelet@google.com> | 2019-09-11 11:16:48 +0000 |
|---|---|---|
| committer | Guillaume Chatelet <gchatelet@google.com> | 2019-09-11 11:16:48 +0000 |
| commit | 48904e9452de81375bd55d830d08e51cc8f2ec7e (patch) | |
| tree | 870ff19fbb173ec430372a5abbf06d4b27bc3836 | |
| parent | d811d9115b0b2d004a568e8ebdb37ba0ea6397d1 (diff) | |
| download | bcm5719-llvm-48904e9452de81375bd55d830d08e51cc8f2ec7e.tar.gz bcm5719-llvm-48904e9452de81375bd55d830d08e51cc8f2ec7e.zip | |
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
649 files changed, 2564 insertions, 2568 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index b6c08f2bae7..be685afdba0 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -277,7 +277,7 @@ class MachineFunction { unsigned FunctionNumber; /// Alignment - The alignment of the function. - unsigned LogAlignment; + llvm::Align Alignment; /// ExposesReturnsTwice - True if the function calls setjmp or related /// functions with attribute "returns twice", but doesn't have @@ -508,16 +508,16 @@ public: const WinEHFuncInfo *getWinEHFuncInfo() const { return WinEHInfo; } WinEHFuncInfo *getWinEHFuncInfo() { return WinEHInfo; } - /// getLogAlignment - Return the alignment of the function. - unsigned getLogAlignment() const { return LogAlignment; } + /// getAlignment - Return the alignment of the function. + llvm::Align getAlignment() const { return Alignment; } - /// setLogAlignment - Set the alignment of the function. - void setLogAlignment(unsigned A) { LogAlignment = A; } + /// setAlignment - Set the alignment of the function. + void setAlignment(llvm::Align A) { Alignment = A; } - /// ensureAlignment - Make sure the function is at least 1 << A bytes aligned. - void ensureLogAlignment(unsigned A) { - if (LogAlignment < A) - LogAlignment = A; + /// ensureAlignment - Make sure the function is at least A bytes aligned. + void ensureAlignment(llvm::Align A) { + if (Alignment < A) + Alignment = A; } /// exposesReturnsTwice - Returns true if the function calls setjmp or diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index cd37eb38bc6..cf47196d041 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -1583,14 +1583,10 @@ public: } /// Return the minimum function alignment. - unsigned getMinFunctionLogAlignment() const { - return Log2(MinFunctionAlignment); - } + llvm::Align getMinFunctionAlignment() const { return MinFunctionAlignment; } /// Return the preferred function alignment. - unsigned getPrefFunctionLogAlignment() const { - return Log2(PrefFunctionAlignment); - } + llvm::Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; } /// Return the preferred loop alignment. virtual llvm::Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const { diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index bf0be8ecee9..077f4ac73ca 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -667,7 +667,7 @@ void AsmPrinter::EmitFunctionHeader() { EmitLinkage(&F, CurrentFnSym); if (MAI->hasFunctionAlignment()) - EmitAlignment(MF->getLogAlignment(), &F); + EmitAlignment(Log2(MF->getAlignment()), &F); if (MAI->hasDotTypeDotSizeDirective()) OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_ELF_TypeFunction); diff --git a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp index ef5aa0499e1..4f561771723 100644 --- a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp @@ -204,7 +204,7 @@ void WinException::beginFunclet(const MachineBasicBlock &MBB, // We want our funclet's entry point to be aligned such that no nops will be // present after the label. Asm->EmitAlignment( - std::max(Asm->MF->getLogAlignment(), MBB.getLogAlignment()), &F); + Log2(std::max(Asm->MF->getAlignment(), MBB.getAlignment())), &F); // Now that we've emitted the alignment directive, point at our funclet. Asm->OutStreamer->EmitLabel(Sym); diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp index 4ee61cff4b4..d027d5b154e 100644 --- a/llvm/lib/CodeGen/BranchRelaxation.cpp +++ b/llvm/lib/CodeGen/BranchRelaxation.cpp @@ -64,19 +64,18 @@ class BranchRelaxation : public MachineFunctionPass { /// Compute the offset immediately following this block. \p MBB is the next /// block. unsigned postOffset(const MachineBasicBlock &MBB) const { - unsigned PO = Offset + Size; - unsigned LogAlign = MBB.getLogAlignment(); - if (LogAlign == 0) + const unsigned PO = Offset + Size; + const llvm::Align Align = MBB.getAlignment(); + if (Align == 1) return PO; - unsigned AlignAmt = 1 << LogAlign; - unsigned ParentLogAlign = MBB.getParent()->getLogAlignment(); - if (LogAlign <= ParentLogAlign) - return PO + OffsetToAlignment(PO, AlignAmt); + const llvm::Align ParentAlign = MBB.getParent()->getAlignment(); + if (Align <= ParentAlign) + return PO + OffsetToAlignment(PO, Align.value()); // The alignment of this MBB is larger than the function's alignment, so we // can't tell whether or not it will insert nops. Assume that it will. - return PO + AlignAmt + OffsetToAlignment(PO, AlignAmt); + return PO + Align.value() + OffsetToAlignment(PO, Align.value()); } }; diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 2dd4fd3b9b7..72d3d1d14e9 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -393,7 +393,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF, } if (YamlMF.Alignment) - MF.setLogAlignment(Log2_32(YamlMF.Alignment)); + MF.setAlignment(llvm::Align(YamlMF.Alignment)); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); MF.setHasWinCFI(YamlMF.HasWinCFI); diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 18efe1f80eb..415f28b094b 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -197,7 +197,7 @@ void MIRPrinter::print(const MachineFunction &MF) { yaml::MachineFunction YamlMF; YamlMF.Name = MF.getName(); - YamlMF.Alignment = 1UL << MF.getLogAlignment(); + YamlMF.Alignment = MF.getAlignment().value(); YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); YamlMF.HasWinCFI = MF.hasWinCFI(); diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index d136ebd437f..832895e2c92 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -173,16 +173,16 @@ void MachineFunction::init() { FrameInfo->ensureMaxAlignment(F.getFnStackAlignment()); ConstantPool = new (Allocator) MachineConstantPool(getDataLayout()); - LogAlignment = STI->getTargetLowering()->getMinFunctionLogAlignment(); + Alignment = STI->getTargetLowering()->getMinFunctionAlignment(); // FIXME: Shouldn't use pref alignment if explicit alignment is set on F. // FIXME: Use Function::hasOptSize(). if (!F.hasFnAttribute(Attribute::OptimizeForSize)) - LogAlignment = std::max( - LogAlignment, STI->getTargetLowering()->getPrefFunctionLogAlignment()); + Alignment = std::max(Alignment, + STI->getTargetLowering()->getPrefFunctionAlignment()); if (AlignAllFunctions) - LogAlignment = AlignAllFunctions; + Alignment = llvm::Align(1ULL << AlignAllFunctions); JumpTableInfo = nullptr; diff --git a/llvm/lib/CodeGen/PatchableFunction.cpp b/llvm/lib/CodeGen/PatchableFunction.cpp index 07f88597fe6..9d7605f078f 100644 --- a/llvm/lib/CodeGen/PatchableFunction.cpp +++ b/llvm/lib/CodeGen/PatchableFunction.cpp @@ -78,7 +78,7 @@ bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) { MIB.add(MO); FirstActualI->eraseFromParent(); - MF.ensureLogAlignment(4); + MF.ensureAlignment(llvm::Align(16)); return true; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 12118e6f5b3..1e3c7edc63f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -417,7 +417,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // The starting address of all shader programs must be 256 bytes aligned. // Regular functions just need the basic required instruction alignment. - MF.setLogAlignment(MFI->isEntryFunction() ? 8 : 2); + MF.setAlignment(MFI->isEntryFunction() ? llvm::Align(256) : llvm::Align(4)); SetupMachineFunction(MF); diff --git a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp index 7918f6bd57c..42158151b64 100644 --- a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp @@ -104,7 +104,7 @@ bool R600AsmPrinter::runOnMachineFunction(MachineFunction &MF) { // Functions needs to be cacheline (256B) aligned. - MF.ensureLogAlignment(8); + MF.ensureAlignment(llvm::Align(256)); SetupMachineFunction(MF); diff --git a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h index f59b0ae65db..997327fd1b8 100644 --- a/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h +++ b/llvm/lib/Target/ARC/ARCMachineFunctionInfo.h @@ -34,8 +34,8 @@ public: explicit ARCFunctionInfo(MachineFunction &MF) : ReturnStackOffsetSet(false), VarArgsFrameIndex(0), ReturnStackOffset(-1U), MaxCallStackReq(0) { - // Functions are 4-byte (2**2) aligned. - MF.setLogAlignment(2); + // Functions are 4-byte aligned. + MF.setAlignment(llvm::Align(4)); } ~ARCFunctionInfo() {} diff --git a/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp b/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp index d8ca5fdda80..a8bdefa9193 100644 --- a/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp @@ -63,7 +63,7 @@ void ARMBasicBlockUtils::computeBlockSize(MachineBasicBlock *MBB) { // tBR_JTr contains a .align 2 directive. if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) { BBI.PostAlign = 2; - MBB->getParent()->ensureLogAlignment(2); + MBB->getParent()->ensureAlignment(llvm::Align(4)); } } diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index ae62d9789bb..9d3e820f96c 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -396,7 +396,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { // Functions with jump tables need an alignment of 4 because they use the ADR // instruction, which aligns the PC to 4 bytes before adding an offset. if (!T2JumpTables.empty()) - MF->ensureLogAlignment(2); + MF->ensureAlignment(llvm::Align(4)); /// Remove dead constant pool entries. MadeChange |= removeUnusedCPEntries(); @@ -493,7 +493,7 @@ ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) // The function needs to be as aligned as the basic blocks. The linker may // move functions around based on their alignment. - MF->ensureLogAlignment(BB->getLogAlignment()); + MF->ensureAlignment(BB->getAlignment()); // Order the entries in BB by descending alignment. That ensures correct // alignment of all entries as long as BB is sufficiently aligned. Keep @@ -686,7 +686,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) { BBInfoVector &BBInfo = BBUtils->getBBInfo(); // The known bits of the entry block offset are determined by the function // alignment. - BBInfo.front().KnownBits = MF->getLogAlignment(); + BBInfo.front().KnownBits = Log2(MF->getAlignment()); // Compute block offsets and known bits. BBUtils->adjustBBOffsetsAfter(&MF->front()); @@ -1041,7 +1041,8 @@ bool ARMConstantIslands::isWaterInRange(unsigned UserOffset, // the offset of the instruction. Also account for unknown alignment padding // in blocks between CPE and the user. if (CPEOffset < UserOffset) - UserOffset += Growth + UnknownPadding(MF->getLogAlignment(), CPELogAlign); + UserOffset += + Growth + UnknownPadding(Log2(MF->getAlignment()), CPELogAlign); } else // CPE fits in existing padding. Growth = 0; @@ -1316,7 +1317,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, // Try to split the block so it's fully aligned. Compute the latest split // point where we can add a 4-byte branch instruction, and then align to // LogAlign which is the largest possible alignment in the function. - unsigned LogAlign = MF->getLogAlignment(); + unsigned LogAlign = Log2(MF->getAlignment()); assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry"); unsigned KnownBits = UserBBI.internalKnownBits(); unsigned UPad = UnknownPadding(LogAlign, KnownBits); diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 750d0c5d463..8840a4938c9 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -400,7 +400,8 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() { // NaCl sandboxing requires that indirect call instructions are masked. // This means that function entry points should be bundle-aligned. if (Subtarget->isTargetNaCl()) - EmitAlignment(std::max(MF->getLogAlignment(), MIPS_NACL_BUNDLE_LOG_ALIGN)); + EmitAlignment( + std::max(Log2(MF->getAlignment()), MIPS_NACL_BUNDLE_LOG_ALIGN)); if (Subtarget->inMicroMipsMode()) { TS.emitDirectiveSetMicroMips(); diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 8907a72ac87..4cd64c67239 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -542,7 +542,7 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { // The function needs to be as aligned as the basic blocks. The linker may // move functions around based on their alignment. - MF->ensureLogAlignment(BB->getLogAlignment()); + MF->ensureAlignment(BB->getAlignment()); // Order the entries in BB by descending alignment. That ensures correct // alignment of all entries as long as BB is sufficiently aligned. Keep @@ -1259,7 +1259,7 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, // Try to split the block so it's fully aligned. Compute the latest split // point where we can add a 4-byte branch instruction, and then align to // LogAlign which is the largest possible alignment in the function. - unsigned LogAlign = MF->getLogAlignment(); + unsigned LogAlign = Log2(MF->getAlignment()); assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry"); unsigned BaseInsertOffset = UserOffset + U.getMaxDisp(); LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x", diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp index 353a3481132..6b95d0d0ce7 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -81,21 +81,20 @@ FunctionPass *llvm::createPPCBranchSelectionPass() { /// original Offset. unsigned PPCBSel::GetAlignmentAdjustment(MachineBasicBlock &MBB, unsigned Offset) { - unsigned LogAlign = MBB.getLogAlignment(); - if (!LogAlign) + const llvm::Align Align = MBB.getAlignment(); + if (Align == 1) return 0; - unsigned AlignAmt = 1 << LogAlign; - unsigned ParentLogAlign = MBB.getParent()->getLogAlignment(); + const llvm::Align ParentAlign = MBB.getParent()->getAlignment(); - if (LogAlign <= ParentLogAlign) - return OffsetToAlignment(Offset, AlignAmt); + if (Align <= ParentAlign) + return OffsetToAlignment(Offset, Align.value()); // The alignment of this MBB is larger than the function's alignment, so we // can't tell whether or not it will insert nops. Assume that it will. if (FirstImpreciseBlock < 0) FirstImpreciseBlock = MBB.getNumber(); - return AlignAmt + OffsetToAlignment(Offset, AlignAmt); + return Align.value() + OffsetToAlignment(Offset, Align.value()); } /// We need to be careful about the offset of the first block in the function diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp index 2b2c80cdd2e..452c439e668 100644 --- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp +++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp @@ -276,7 +276,7 @@ uint64_t SystemZLongBranch::initMBBInfo() { Terminators.clear(); Terminators.reserve(NumBlocks); - BlockPosition Position(MF->getLogAlignment()); + BlockPosition Position(Log2(MF->getAlignment())); for (unsigned I = 0; I < NumBlocks; ++I) { MachineBasicBlock *MBB = MF->getBlockNumbered(I); MBBInfo &Block = MBBs[I]; @@ -340,7 +340,7 @@ bool SystemZLongBranch::mustRelaxABranch() { // must be long. void SystemZLongBranch::setWorstCaseAddresses() { SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin(); - BlockPosition Position(MF->getLogAlignment()); + BlockPosition Position(Log2(MF->getAlignment())); for (auto &Block : MBBs) { skipNonTerminators(Position, Block); for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { @@ -441,7 +441,7 @@ void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) { // Run a shortening pass and relax any branches that need to be relaxed. void SystemZLongBranch::relaxBranches() { SmallVector<TerminatorInfo, 16>::iterator TI = Terminators.begin(); - BlockPosition Position(MF->getLogAlignment()); + BlockPosition Position(Log2(MF->getAlignment())); for (auto &Block : MBBs) { skipNonTerminators(Position, Block); for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir index ab4b68de2a2..b1553237a07 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -793,7 +793,7 @@ body: | # Make sure we map FPEXT on FPR register bank. # CHECK-LABEL: name: fp16Ext32 name: fp16Ext32 -alignment: 2 +alignment: 4 legalized: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } @@ -828,7 +828,7 @@ body: | # Make sure we map FPEXT on FPR register bank. # CHECK-LABEL: name: fp16Ext64 name: fp16Ext64 -alignment: 2 +alignment: 4 legalized: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } @@ -863,7 +863,7 @@ body: | # Make sure we map FPEXT on FPR register bank. # CHECK-LABEL: name: fp32Ext64 name: fp32Ext64 -alignment: 2 +alignment: 4 legalized: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } @@ -897,7 +897,7 @@ body: | # CHECK: %0:fpr(s16) = COPY $h0 # CHECK-NEXT: $h0 = COPY %0(s16) name: passFp16 -alignment: 2 +alignment: 4 legalized: true registers: - { id: 0, class: _ } @@ -931,7 +931,7 @@ body: | # CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr) # CHECK-NEXT: $h0 = COPY %2(s16) name: passFp16ViaAllocas -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir index 1671a2692bc..04d34a9faec 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-anyext-crash.mir @@ -17,7 +17,7 @@ ... --- name: test_anyext_crash -alignment: 2 +alignment: 4 legalized: false registers: - { id: 0, class: _, preferred-register: '' } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir index 15b3e74e297..52383f6cd5d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir @@ -14,7 +14,7 @@ ... --- name: fcmp_more_than_one_user_no_fold -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -50,7 +50,7 @@ body: | ... --- name: using_icmp -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -81,7 +81,7 @@ body: | ... --- name: foeq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -111,7 +111,7 @@ body: | ... --- name: fueq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -147,7 +147,7 @@ body: | ... --- name: fone -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -183,7 +183,7 @@ body: | ... --- name: fune -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -213,7 +213,7 @@ body: | ... --- name: doeq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -243,7 +243,7 @@ body: | ... --- name: dueq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -279,7 +279,7 @@ body: | ... --- name: done -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -315,7 +315,7 @@ body: | ... --- name: dune -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -345,7 +345,7 @@ body: | ... --- name: copy_from_physreg -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir index 53bf0a32af4..060db2c99ee 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir @@ -9,7 +9,7 @@ ... --- name: eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -38,7 +38,7 @@ body: | ... --- name: using_fcmp -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir index 304f42c050c..d7aef52744b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir @@ -15,7 +15,7 @@ ... --- name: x -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir index 78b989f0556..193b278b6b2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir @@ -21,7 +21,7 @@ ... --- name: fp16_to_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -73,7 +73,7 @@ body: | --- name: gpr_to_fp16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -101,7 +101,7 @@ body: | ... --- name: gpr_to_fp16_physreg -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir index 8ac50f7f0e7..064c74a434f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir @@ -36,7 +36,7 @@ ... --- name: test_memcpy1 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -63,7 +63,7 @@ body: | ... --- name: test_memcpy2_const -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -110,7 +110,7 @@ body: | ... --- name: test_memcpy3_const_arrays_unaligned -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir index 8dbd1310bd0..9dc50c979fa 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir @@ -44,7 +44,7 @@ ... --- name: test_memmove1 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -66,7 +66,7 @@ body: | ... --- name: test_memmove2_const -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -100,7 +100,7 @@ body: | ... --- name: test_memmove3_const_toolarge -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -122,7 +122,7 @@ body: | ... --- name: test_memmove4_const_unaligned -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir index 1326ee3dff0..209dae31e79 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir @@ -41,7 +41,7 @@ ... --- name: test_ms1 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -67,7 +67,7 @@ body: | ... --- name: test_ms2_const -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -96,7 +96,7 @@ body: | ... --- name: test_ms3_const_both -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -120,7 +120,7 @@ body: | ... --- name: test_ms4_const_both_unaligned -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir index 2eff8b8be8b..873ac6d672f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir @@ -27,7 +27,7 @@ ... --- name: test_small_memcpy -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -59,7 +59,7 @@ body: | ... --- name: test_large_memcpy -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir index 4fd81981b49..abab5192ebb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir @@ -128,7 +128,7 @@ body: | ... --- name: add_v8i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -151,7 +151,7 @@ body: | ... --- name: add_v16i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir index 60b47db98ed..e09e049ecdd 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir @@ -17,7 +17,7 @@ ... --- name: test_blockaddress -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir index bb0063b167f..982bd24c77c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir @@ -12,7 +12,7 @@ ... --- name: test_v8f16.ceil -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -55,7 +55,7 @@ body: | ... --- name: test_v4f16.ceil -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir index abd391efaf9..06d7b18c673 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir @@ -40,7 +40,7 @@ body: | ... --- name: test_s128 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; CHECK-LABEL: name: test_s128 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir index a2e8ee17232..552c7f3c7d9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.cos -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -57,7 +57,7 @@ body: | ... --- name: test_v8f16.cos -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -91,7 +91,7 @@ body: | ... --- name: test_v2f32.cos -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -125,7 +125,7 @@ body: | ... --- name: test_v4f32.cos -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -170,7 +170,7 @@ body: | ... --- name: test_v2f64.cos -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -204,7 +204,7 @@ body: | ... --- name: test_cos_half -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir index 2ec40881aea..68a70e00c91 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir @@ -41,7 +41,7 @@ body: | ... --- name: sdiv_v4s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir index 44c6e2cde36..ff750a16eec 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir @@ -22,7 +22,7 @@ ... --- name: test_simple_alloca -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$w0' } @@ -68,7 +68,7 @@ body: | ... --- name: test_aligned_alloca -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$w0' } @@ -116,7 +116,7 @@ body: | ... --- name: test_natural_alloca -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$w0' } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir index d299d6e7b6d..ee8ebfe868e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.exp -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -57,7 +57,7 @@ body: | ... --- name: test_v8f16.exp -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -91,7 +91,7 @@ body: | ... --- name: test_v2f32.exp -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -125,7 +125,7 @@ body: | ... --- name: test_v4f32.exp -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -170,7 +170,7 @@ body: | ... --- name: test_v2f64.exp -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -204,7 +204,7 @@ body: | ... --- name: test_exp_half -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir index e08bf29f3c7..41746bc3165 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir @@ -176,7 +176,7 @@ body: | ... --- name: test_zext_v8s16_from_v8s8 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -196,7 +196,7 @@ body: | ... --- name: test_sext_v8s16_from_v8s8 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -216,7 +216,7 @@ body: | ... --- name: test_anyext_v8s16_from_v8s8 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -236,7 +236,7 @@ body: | ... --- name: test_zext_v4s32_from_v4s16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -257,7 +257,7 @@ body: | ... --- name: test_sext_v4s32_from_v4s16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -278,7 +278,7 @@ body: | ... --- name: test_anyext_v4s32_from_v4s16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -299,7 +299,7 @@ body: | ... --- name: test_zext_v2s64_from_v2s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -323,7 +323,7 @@ body: | ... --- name: test_sext_v2s64_from_v2s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -347,7 +347,7 @@ body: | ... --- name: test_anyext_v2s64_from_v2s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir index d0baaa58e28..4e2a8547204 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir @@ -5,7 +5,7 @@ ... --- name: test_v4f16.exp2 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -53,7 +53,7 @@ body: | ... --- name: test_v8f16.exp2 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -129,7 +129,7 @@ body: | ... --- name: test_v2f32.exp2 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -159,7 +159,7 @@ body: | ... --- name: test_v4f32.exp2 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -199,7 +199,7 @@ body: | ... --- name: test_v2f64.exp2 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -229,7 +229,7 @@ body: | ... --- name: test_exp2_half -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fma.mir index 1c3d1f0f03f..3388ab97dc3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fma.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fma.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.fma -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -60,7 +60,7 @@ body: | ... --- name: test_v8f16.fma -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -136,7 +136,7 @@ body: | ... --- name: test_v2f32.fma -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -169,7 +169,7 @@ body: | ... --- name: test_v4f32.fma -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -202,7 +202,7 @@ body: | ... --- name: test_v2f64.fma -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir index 5d6733b23bc..def81870ff4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-frint.mir @@ -3,7 +3,7 @@ # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -global-isel %s -o - | FileCheck %s --check-prefix=FP16 name: test_f16.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -18,7 +18,7 @@ body: | ... --- name: test_f32.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -45,7 +45,7 @@ body: | ... --- name: test_f64.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -72,7 +72,7 @@ body: | ... --- name: test_v4f32.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -99,7 +99,7 @@ body: | ... --- name: test_v2f64.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -126,7 +126,7 @@ body: | ... --- name: test_v4f16.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -166,7 +166,7 @@ body: | ... --- name: test_v8f16.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -218,7 +218,7 @@ body: | ... --- name: test_v2f32.rint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir index 83ef420c1a8..91842a70158 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-round.mir @@ -6,7 +6,7 @@ ... --- name: test_f16.round -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -35,7 +35,7 @@ body: | ... --- name: test_f32.round -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -62,7 +62,7 @@ body: | ... --- name: test_f64.round -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -89,7 +89,7 @@ body: | ... --- name: test_v8f16.round -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -141,7 +141,7 @@ body: | ... --- name: test_v4f16.round -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -184,7 +184,7 @@ body: | ... --- name: test_v2f32.round -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -214,7 +214,7 @@ body: | ... --- name: test_v4f32.round -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -244,7 +244,7 @@ body: | ... --- name: test_v2f64.round -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-trunc.mir index c552a55323a..b6a98a94d0f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-trunc.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-trunc.mir @@ -5,7 +5,7 @@ ... --- name: test_f16.intrinsic_trunc -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -32,7 +32,7 @@ body: | ... --- name: test_v4f16.intrinsic_trunc -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -72,7 +72,7 @@ body: | ... --- name: test_v8f16.intrinsic_trunc -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -124,7 +124,7 @@ body: | ... --- name: test_v2f32.intrinsic_trunc -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -151,7 +151,7 @@ body: | ... --- name: test_v4f32.intrinsic_trunc -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -178,7 +178,7 @@ body: | ... --- name: test_v2f64.intrinsic_trunc -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir index fb0bc27f8e1..7661626f6c1 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir @@ -21,7 +21,7 @@ --- name: broken -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir index 3956f3a6c35..0b5b7b440f2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir @@ -24,7 +24,7 @@ --- name: broken -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir index 518212aec83..6d50898117c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir @@ -19,7 +19,7 @@ ... --- name: store_v2p0 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -41,7 +41,7 @@ body: | ... --- name: load_v2p0 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -63,7 +63,7 @@ body: | ... --- name: load_v2p1 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir index 5f7fa7ba6d9..504fb1a12b5 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir @@ -151,7 +151,7 @@ body: | ... --- name: store_4xi16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -172,7 +172,7 @@ body: | ... --- name: store_4xi32 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -193,7 +193,7 @@ body: | ... --- name: store_8xi16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -214,7 +214,7 @@ body: | ... --- name: store_16xi8 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -235,7 +235,7 @@ body: | ... --- name: load_4xi16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -256,7 +256,7 @@ body: | ... --- name: load_4xi32 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -277,7 +277,7 @@ body: | ... --- name: load_8xi16 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -298,7 +298,7 @@ body: | ... --- name: load_16xi8 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -319,7 +319,7 @@ body: | ... --- name: load_8xi8 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir index c70f48b30ca..f8ccd852a0b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.log -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -57,7 +57,7 @@ body: | ... --- name: test_v8f16.log -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -91,7 +91,7 @@ body: | ... --- name: test_v2f32.log -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -125,7 +125,7 @@ body: | ... --- name: test_v4f32.log -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -170,7 +170,7 @@ body: | ... --- name: test_v2f64.log -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -204,7 +204,7 @@ body: | ... --- name: test_log_half -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir index 08e1a4f53d1..509b0a3bd50 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.log10 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -57,7 +57,7 @@ body: | ... --- name: test_v8f16.log10 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -91,7 +91,7 @@ body: | ... --- name: test_v2f32.log10 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -125,7 +125,7 @@ body: | ... --- name: test_v4f32.log10 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -170,7 +170,7 @@ body: | ... --- name: test_v2f64.log10 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -204,7 +204,7 @@ body: | ... --- name: test_log10_half -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir index 9ec78992f0e..a4b05c5498d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.log2 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -57,7 +57,7 @@ body: | ... --- name: test_v8f16.log2 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -91,7 +91,7 @@ body: | ... --- name: test_v2f32.log2 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -125,7 +125,7 @@ body: | ... --- name: test_v4f32.log2 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -170,7 +170,7 @@ body: | ... --- name: test_v2f64.log2 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -204,7 +204,7 @@ body: | ... --- name: test_log2_half -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir index cf18cce5087..8d301348844 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir @@ -5,7 +5,7 @@ ... --- name: test_v4f16.nearbyint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -45,7 +45,7 @@ body: | ... --- name: test_v8f16.nearbyint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -97,7 +97,7 @@ body: | ... --- name: test_v2f32.nearbyint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -124,7 +124,7 @@ body: | ... --- name: test_v2f64.nearbyint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -151,7 +151,7 @@ body: | ... --- name: test_f32.nearbyint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -178,7 +178,7 @@ body: | ... --- name: test_f64.nearbyint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -205,7 +205,7 @@ body: | ... --- name: test_f16.nearbyint -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir index 559ddada95d..7dbb1312603 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir @@ -13,7 +13,7 @@ ... --- name: load_store_test -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir index 51f61ea773c..a92b06446cc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir @@ -43,7 +43,7 @@ ... --- name: legalize_phi -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -130,7 +130,7 @@ body: | ... --- name: legalize_phi_ptr -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -184,7 +184,7 @@ body: | ... --- name: legalize_phi_empty -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -270,7 +270,7 @@ body: | ... --- name: legalize_phi_loop -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -338,7 +338,7 @@ body: | ... --- name: legalize_phi_cycle -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -395,7 +395,7 @@ body: | ... --- name: legalize_phi_same_bb -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -496,7 +496,7 @@ body: | ... --- name: legalize_phi_diff_bb -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir index a681bafca8b..bd5995fb23c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir @@ -35,7 +35,7 @@ body: | ... --- name: test_v4f16.pow -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -95,7 +95,7 @@ body: | ... --- name: test_v8f16.pow -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -191,7 +191,7 @@ body: | ... --- name: test_v2f32.pow -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -227,7 +227,7 @@ body: | ... --- name: test_v4f32.pow -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -275,7 +275,7 @@ body: | ... --- name: test_v2f64.pow -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir index 5f2f011a787..6fcc926cab8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir @@ -11,7 +11,7 @@ ... --- name: udiv_test -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$x0' } @@ -52,7 +52,7 @@ body: | ... --- name: sdiv_test -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$x0' } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir index f1bd03e71f6..529c7846484 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir @@ -3,7 +3,7 @@ ... --- name: v2s64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: @@ -37,7 +37,7 @@ body: | ... --- name: v2s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir index 9d95c35f05a..7b4ae3d56ab 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir @@ -2,7 +2,7 @@ # RUN: llc -mtriple=aarch64 -O0 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s --- name: shuffle_v4i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1: @@ -24,7 +24,7 @@ body: | ... --- name: shuffle_v2i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1: @@ -46,7 +46,7 @@ body: | ... --- name: shuffle_1elt_mask -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir index f1fec69fa41..225bc84add7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.sin -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -57,7 +57,7 @@ body: | ... --- name: test_v8f16.sin -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -91,7 +91,7 @@ body: | ... --- name: test_v2f32.sin -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -125,7 +125,7 @@ body: | ... --- name: test_v4f32.sin -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -170,7 +170,7 @@ body: | ... --- name: test_v2f64.sin -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -204,7 +204,7 @@ body: | ... --- name: test_sin_half -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir index 9a6fe808ea3..ce9093b9213 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sqrt.mir @@ -12,7 +12,7 @@ ... --- name: test_v8f16.sqrt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -55,7 +55,7 @@ body: | ... --- name: test_v4f16.sqrt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir index b1800305022..ce078624a98 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-icmp.mir @@ -2,7 +2,7 @@ # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s --- name: test_v2i64_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -32,7 +32,7 @@ body: | ... --- name: test_v4i32_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -62,7 +62,7 @@ body: | ... --- name: test_v2i32_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -92,7 +92,7 @@ body: | ... --- name: test_v8i16_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -122,7 +122,7 @@ body: | ... --- name: test_v4i16_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -152,7 +152,7 @@ body: | ... --- name: test_v16i8_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -182,7 +182,7 @@ body: | ... --- name: test_v8i8_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -212,7 +212,7 @@ body: | ... --- name: test_v2i64_ugt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -242,7 +242,7 @@ body: | ... --- name: test_v4i32_ugt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -272,7 +272,7 @@ body: | ... --- name: test_v2i32_ugt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -302,7 +302,7 @@ body: | ... --- name: test_v8i16_ugt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -332,7 +332,7 @@ body: | ... --- name: test_v4i16_ugt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -362,7 +362,7 @@ body: | ... --- name: test_v16i8_ugt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -392,7 +392,7 @@ body: | ... --- name: test_v8i8_ugt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -422,7 +422,7 @@ body: | ... --- name: test_v2i64_uge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -452,7 +452,7 @@ body: | ... --- name: test_v4i32_uge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -482,7 +482,7 @@ body: | ... --- name: test_v2i32_uge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -512,7 +512,7 @@ body: | ... --- name: test_v8i16_uge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -542,7 +542,7 @@ body: | ... --- name: test_v4i16_uge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -572,7 +572,7 @@ body: | ... --- name: test_v16i8_uge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -602,7 +602,7 @@ body: | ... --- name: test_v8i8_uge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -632,7 +632,7 @@ body: | ... --- name: test_v2i64_ult -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -662,7 +662,7 @@ body: | ... --- name: test_v4i32_ult -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -692,7 +692,7 @@ body: | ... --- name: test_v2i32_ult -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -722,7 +722,7 @@ body: | ... --- name: test_v8i16_ult -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -752,7 +752,7 @@ body: | ... --- name: test_v4i16_ult -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -782,7 +782,7 @@ body: | ... --- name: test_v16i8_ult -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -812,7 +812,7 @@ body: | ... --- name: test_v8i8_ult -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -842,7 +842,7 @@ body: | ... --- name: test_v2i64_ule -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -872,7 +872,7 @@ body: | ... --- name: test_v4i32_ule -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -902,7 +902,7 @@ body: | ... --- name: test_v2i32_ule -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -932,7 +932,7 @@ body: | ... --- name: test_v8i16_ule -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -962,7 +962,7 @@ body: | ... --- name: test_v4i16_ule -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -992,7 +992,7 @@ body: | ... --- name: test_v16i8_ule -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1022,7 +1022,7 @@ body: | ... --- name: test_v8i8_ule -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1052,7 +1052,7 @@ body: | ... --- name: test_v2i64_sgt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1082,7 +1082,7 @@ body: | ... --- name: test_v4i32_sgt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1112,7 +1112,7 @@ body: | ... --- name: test_v2i32_sgt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1142,7 +1142,7 @@ body: | ... --- name: test_v8i16_sgt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1172,7 +1172,7 @@ body: | ... --- name: test_v4i16_sgt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1202,7 +1202,7 @@ body: | ... --- name: test_v16i8_sgt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1232,7 +1232,7 @@ body: | ... --- name: test_v8i8_sgt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1262,7 +1262,7 @@ body: | ... --- name: test_v2i64_sge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1292,7 +1292,7 @@ body: | ... --- name: test_v4i32_sge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1322,7 +1322,7 @@ body: | ... --- name: test_v2i32_sge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1352,7 +1352,7 @@ body: | ... --- name: test_v8i16_sge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1382,7 +1382,7 @@ body: | ... --- name: test_v4i16_sge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1412,7 +1412,7 @@ body: | ... --- name: test_v16i8_sge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1442,7 +1442,7 @@ body: | ... --- name: test_v8i8_sge -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1472,7 +1472,7 @@ body: | ... --- name: test_v2i64_slt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1502,7 +1502,7 @@ body: | ... --- name: test_v4i32_slt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1532,7 +1532,7 @@ body: | ... --- name: test_v2i32_slt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1562,7 +1562,7 @@ body: | ... --- name: test_v8i16_slt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1592,7 +1592,7 @@ body: | ... --- name: test_v4i16_slt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1622,7 +1622,7 @@ body: | ... --- name: test_v16i8_slt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1652,7 +1652,7 @@ body: | ... --- name: test_v8i8_slt -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1682,7 +1682,7 @@ body: | ... --- name: test_v2i64_sle -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1712,7 +1712,7 @@ body: | ... --- name: test_v4i32_sle -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1742,7 +1742,7 @@ body: | ... --- name: test_v2i32_sle -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1772,7 +1772,7 @@ body: | ... --- name: test_v8i16_sle -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1802,7 +1802,7 @@ body: | ... --- name: test_v4i16_sle -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1832,7 +1832,7 @@ body: | ... --- name: test_v16i8_sle -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1862,7 +1862,7 @@ body: | ... --- name: test_v8i8_sle -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1892,7 +1892,7 @@ body: | ... --- name: test_v2p0_eq -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir index 28d7169e713..6ccddd99a47 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir @@ -4,7 +4,7 @@ # This test checks we don't crash when doing zext(trunc) legalizer combines. --- name: zext_trunc_dead_inst_crash -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; CHECK-LABEL: name: zext_trunc_dead_inst_crash diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir index 6431cf1f5a6..03909813972 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir @@ -29,7 +29,7 @@ --- name: ldrxrox_breg_oreg -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -55,7 +55,7 @@ body: | --- name: ldrdrox_breg_oreg -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -79,7 +79,7 @@ body: | ... --- name: more_than_one_use -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -111,7 +111,7 @@ body: | ... --- name: ldrxrox_shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -138,7 +138,7 @@ body: | ... --- name: ldrdrox_shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -165,7 +165,7 @@ body: | ... --- name: ldrxrox_mul_rhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -192,7 +192,7 @@ body: | ... --- name: ldrdrox_mul_rhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -219,7 +219,7 @@ body: | ... --- name: ldrxrox_mul_lhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -246,7 +246,7 @@ body: | ... --- name: ldrdrox_mul_lhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -273,7 +273,7 @@ body: | ... --- name: mul_not_pow_2 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -305,7 +305,7 @@ body: | ... --- name: mul_wrong_pow_2 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -337,7 +337,7 @@ body: | ... --- name: more_than_one_use_shl_1 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -371,7 +371,7 @@ body: | ... --- name: more_than_one_use_shl_2 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -410,7 +410,7 @@ body: | ... --- name: more_than_one_use_shl_lsl_fast -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -443,7 +443,7 @@ body: | ... --- name: more_than_one_use_shl_lsl_slow -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -478,7 +478,7 @@ body: | ... --- name: more_than_one_use_shl_minsize -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -515,7 +515,7 @@ body: | ... --- name: ldrwrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -539,7 +539,7 @@ body: | ... --- name: ldrsrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -563,7 +563,7 @@ body: | ... --- name: ldrhrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -587,7 +587,7 @@ body: | ... --- name: ldbbrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -611,7 +611,7 @@ body: | ... --- name: ldrqrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir index 869b328a752..bfa02814e6b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir @@ -29,7 +29,7 @@ --- # CHECK-LABEL: name: foo name: foo -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir index 67624170661..1eee40dd648 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir @@ -392,7 +392,7 @@ body: | ... --- name: test_inttoptr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir b/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir index 667a7690466..2b69c13174f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir @@ -81,7 +81,7 @@ body: | ... --- name: int_extensions -alignment: 2 +alignment: 4 legalized: false regBankSelected: false selected: false diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir b/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir index d9e4df8cf45..12d346a7d06 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir @@ -13,7 +13,7 @@ ... --- name: ld_zext_i24 -alignment: 2 +alignment: 4 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir index cfc990b2a2c..8d3add417cc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/observer-change-crash.mir @@ -11,7 +11,7 @@ ... --- name: test -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir index 4dbc2e2ad9e..d6bc336323e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir @@ -32,7 +32,7 @@ ... --- name: cmn_s32_rhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -64,7 +64,7 @@ body: | ... --- name: cmn_s32_lhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -96,7 +96,7 @@ body: | ... --- name: no_cmn_s32_rhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -129,7 +129,7 @@ body: | ... --- name: no_cmn_s32_lhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -162,7 +162,7 @@ body: | ... --- name: cmn_s64_rhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -195,7 +195,7 @@ body: | ... --- name: cmn_s64_lhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -228,7 +228,7 @@ body: | ... --- name: no_cmn_s64_rhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -262,7 +262,7 @@ body: | ... --- name: no_cmn_s64_lhs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -296,7 +296,7 @@ body: | ... --- name: tst_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -327,7 +327,7 @@ body: | ... --- name: tst_s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -359,7 +359,7 @@ body: | ... --- name: no_tst_unsigned_compare -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -391,7 +391,7 @@ body: | ... --- name: no_tst_nonzero -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -423,7 +423,7 @@ body: | ... --- name: imm_tst -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -455,7 +455,7 @@ body: | ... --- name: no_imm_tst_not_logical_imm -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -487,7 +487,7 @@ body: | ... --- name: test_physreg_copy -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir index bb8f6a775eb..4c0f13adc56 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir @@ -2,7 +2,7 @@ # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -O1 -verify-machineinstrs %s -o - | FileCheck %s --- name: splat_4xi32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -27,7 +27,7 @@ body: | ... --- name: splat_2xi64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -52,7 +52,7 @@ body: | ... --- name: splat_4xf32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -79,7 +79,7 @@ body: | ... --- name: splat_2xf64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -106,7 +106,7 @@ body: | ... --- name: splat_2xf64_copies -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -137,7 +137,7 @@ body: | ... --- name: not_all_zeros -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir index e8decdc21e5..b77255e4871 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir @@ -10,7 +10,7 @@ ... --- name: test -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir index 496f19edb8a..213b9edf137 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir @@ -2,7 +2,7 @@ # RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s name: v2s32_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true registers: @@ -22,7 +22,7 @@ body: | ... --- name: v4s32_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true registers: @@ -49,7 +49,7 @@ body: | ... --- name: v2s64_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true registers: @@ -76,7 +76,7 @@ body: | ... --- name: v4s16_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir index 22b8da5451a..867e6a0e4da 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir @@ -2,7 +2,7 @@ # RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s --- name: extract_s64_s128 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir index 70482234bd0..8f07c6f6e13 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-fma.mir @@ -5,7 +5,7 @@ --- name: fma_f32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -31,7 +31,7 @@ body: | ... --- name: fma_f64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir index 889bc2ef8c1..eb539aacc4b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir @@ -13,7 +13,7 @@ # 3) The fourth operand should be a GPR, since it's a constant. name: v4s32_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -38,7 +38,7 @@ body: | ... --- name: v4s32_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -63,7 +63,7 @@ body: | ... --- name: v2s64_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -88,7 +88,7 @@ body: | ... --- name: v2s64_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -113,7 +113,7 @@ body: | ... --- name: v2s32_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -138,7 +138,7 @@ body: | ... --- name: v2s32_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir index 3ed50b5c4fd..57e1a4faeca 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-round.mir @@ -6,7 +6,7 @@ ... --- name: test_f16.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -30,7 +30,7 @@ body: | ... --- name: test_f32.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -54,7 +54,7 @@ body: | ... --- name: test_f64.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -78,7 +78,7 @@ body: | ... --- name: test_v8f16.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -102,7 +102,7 @@ body: | ... --- name: test_v4f16.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -126,7 +126,7 @@ body: | ... --- name: test_v2f32.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -150,7 +150,7 @@ body: | ... --- name: test_v4f32.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -174,7 +174,7 @@ body: | ... --- name: test_v2f64.round -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir index d43d3eb5c96..c89cedd2af7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-intrinsic-trunc.mir @@ -4,7 +4,7 @@ ... --- name: test_f32.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -28,7 +28,7 @@ body: | ... --- name: test_f64.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir index ba5d6ffa9e1..e4b510c145d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-nearbyint.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.nearbyint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -26,7 +26,7 @@ body: | ... --- name: test_v8f16.nearbyint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -48,7 +48,7 @@ body: | ... --- name: test_v2f32.nearbyint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -70,7 +70,7 @@ body: | ... --- name: test_v2f64.nearbyint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -92,7 +92,7 @@ body: | ... --- name: test_f32.nearbyint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -114,7 +114,7 @@ body: | ... --- name: test_f64.nearbyint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -136,7 +136,7 @@ body: | ... --- name: test_f16.nearbyint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir index 38aaf18442e..c0fa01e074d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir @@ -4,7 +4,7 @@ ... --- name: select_f32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -32,7 +32,7 @@ body: | ... --- name: select_f64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -60,7 +60,7 @@ body: | ... --- name: two_fpr_inputs_gpr_output -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -94,7 +94,7 @@ body: | ... --- name: one_fpr_input_fpr_output -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -126,7 +126,7 @@ body: | ... --- name: one_fpr_input_gpr_output -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} @@ -158,7 +158,7 @@ body: | ... --- name: two_gpr_input_fpr_output -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true machineFunctionInfo: {} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir index ac31a5ae481..1492808e741 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-trunc-s128.mir @@ -2,7 +2,7 @@ # RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s --- name: trunc_s64_s128 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir index fecc5298898..e41bead422d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir @@ -2,7 +2,7 @@ # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s --- name: build_vec_f16 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir index d1032548090..749a2ff3ca3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir @@ -2,7 +2,7 @@ # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s --- name: unmerge -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: @@ -26,7 +26,7 @@ body: | ... --- name: unmerge_s128 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true frameInfo: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir index 31077507614..707ff0a5663 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir @@ -3,7 +3,7 @@ --- name: add_sext_s32_to_s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -27,7 +27,7 @@ body: | ... --- name: add_and_s32_to_s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: add_sext_s16_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -79,7 +79,7 @@ body: | ... --- name: add_zext_s16_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -104,7 +104,7 @@ body: | ... --- name: add_anyext_s16_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -129,7 +129,7 @@ body: | ... --- name: add_and_s16_to_s32_uxtb -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -154,7 +154,7 @@ body: | ... --- name: add_and_s16_to_s32_uxth -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -179,7 +179,7 @@ body: | ... --- name: add_sext_s8_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -204,7 +204,7 @@ body: | ... --- name: add_zext_s8_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -229,7 +229,7 @@ body: | ... --- name: add_anyext_s8_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -254,7 +254,7 @@ body: | ... --- name: add_sext_with_shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -281,7 +281,7 @@ body: | ... --- name: add_and_with_shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -308,7 +308,7 @@ body: | ... --- name: dont_fold_invalid_mask -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -336,7 +336,7 @@ body: | ... --- name: dont_fold_invalid_shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -364,7 +364,7 @@ body: | ... --- name: sub_sext_s32_to_s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -388,7 +388,7 @@ body: | ... --- name: sub_sext_s16_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -413,7 +413,7 @@ body: | ... --- name: sub_zext_s16_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -438,7 +438,7 @@ body: | ... --- name: sub_anyext_s16_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -463,7 +463,7 @@ body: | ... --- name: sub_and_s16_to_s32_uxtb -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -488,7 +488,7 @@ body: | ... --- name: sub_and_s16_to_s32_uxth -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -512,7 +512,7 @@ body: | RET_ReallyLR implicit $w3 --- name: sub_sext_s8_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -530,7 +530,7 @@ body: | ... --- name: sub_zext_s8_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -555,7 +555,7 @@ body: | ... --- name: sub_anyext_s8_to_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -581,7 +581,7 @@ body: | ... --- name: sub_sext_with_shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -608,7 +608,7 @@ body: | ... --- name: sub_and_with_shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir index 516e0fb267a..c3b63dba88f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir @@ -12,7 +12,7 @@ ... --- name: load_acq_i8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir index 8ab0f6049a9..2c53f6df4d4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir @@ -1072,7 +1072,7 @@ body: | ... --- name: add_v8i16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1101,7 +1101,7 @@ body: | ... --- name: add_v16i8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir index 43e77eba48f..e7b414bad7b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir @@ -20,7 +20,7 @@ ... --- name: test_blockaddress -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir index d1978c2a215..77c03073033 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir @@ -48,7 +48,7 @@ body: | ... --- name: bswap_v4s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -71,7 +71,7 @@ body: | ... --- name: bswap_v2s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -94,7 +94,7 @@ body: | ... --- name: bswap_v2s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir index 124914233eb..d3ec9a87287 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir @@ -25,7 +25,7 @@ ... --- name: test_f32 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -66,7 +66,7 @@ body: | ... --- name: test_f64 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -97,7 +97,7 @@ body: | ... --- name: test_i32 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -132,7 +132,7 @@ body: | ... --- name: test_i64 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -161,7 +161,7 @@ body: | ... --- name: test_p0 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir index c8fd3069d73..131e67335bb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir @@ -119,7 +119,7 @@ body: | ... --- name: test_rhs_inttoptr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -156,7 +156,7 @@ body: | ... --- name: test_rhs_unknown -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir index 2aee3f18bb1..2fdec4a62f6 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir @@ -3,7 +3,7 @@ ... --- name: legal_v4s32_v2s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -36,7 +36,7 @@ body: | ... --- name: legal_v8s16_v4s16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir index 74e490355b0..9873d49b2a3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ctlz.mir @@ -2,7 +2,7 @@ # RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s name: test_v8s8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -24,7 +24,7 @@ body: | ... --- name: test_v4s16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -46,7 +46,7 @@ body: | ... --- name: test_v2s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -68,7 +68,7 @@ body: | ... --- name: test_s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -92,7 +92,7 @@ body: | ... --- name: test_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -115,7 +115,7 @@ body: | ... --- name: test_v16s8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -137,7 +137,7 @@ body: | ... --- name: test_v8s16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -159,7 +159,7 @@ body: | ... --- name: test_v4s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -181,7 +181,7 @@ body: | ... --- name: test_v2s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir index 41f1479a5b5..17cd2ee27fd 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir @@ -3,7 +3,7 @@ ... --- name: v2s32_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -34,7 +34,7 @@ body: | ... --- name: v2s32_fpr_idx0 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -57,7 +57,7 @@ body: | ... --- name: v2s64_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -86,7 +86,7 @@ body: | ... --- name: v4s16_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -117,7 +117,7 @@ body: | ... --- name: v8s16_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -140,7 +140,7 @@ body: | ... --- name: v8s16_fpr_zext -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -164,7 +164,7 @@ body: | ... --- name: v8s16_fpr_sext -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -188,7 +188,7 @@ body: | ... --- name: v8s16_fpr_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir index c3e9ea5bc58..b366c0dea26 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir @@ -6,7 +6,7 @@ ... --- name: zero -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -31,7 +31,7 @@ body: | ... --- name: notzero -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir index bc4ba450c87..c50d808662c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir @@ -4,7 +4,7 @@ ... --- name: test_f16.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -31,7 +31,7 @@ body: | ... --- name: test_v4f16.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -100,7 +100,7 @@ body: | ... --- name: test_v8f16.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir index 192ce50b277..0f3e4cbc6eb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir @@ -4,7 +4,7 @@ ... --- name: test_f16.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -27,7 +27,7 @@ body: | ... --- name: test_f32.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -50,7 +50,7 @@ body: | ... --- name: test_f64.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -73,7 +73,7 @@ body: | ... --- name: test_v4f32.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -96,7 +96,7 @@ body: | ... --- name: test_v2f64.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -119,7 +119,7 @@ body: | ... --- name: test_v4f16.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -142,7 +142,7 @@ body: | ... --- name: test_v8f16.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -165,7 +165,7 @@ body: | ... --- name: test_v2f32.rint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir index a206b1cd028..7890a4c846a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir @@ -2,7 +2,7 @@ # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s name: v4s32_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -29,7 +29,7 @@ body: | ... --- name: v4s32_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: v2s64_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -81,7 +81,7 @@ body: | ... --- name: v2s64_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -106,7 +106,7 @@ body: | ... --- name: v2s32_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -136,7 +136,7 @@ body: | ... --- name: v2s32_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir index 90de1f6df2c..2d51277ff28 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -75,7 +75,7 @@ body: | --- name: anyext_v8s16_from_v8s8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -101,7 +101,7 @@ body: | --- name: anyext_v4s32_from_v4s16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -127,7 +127,7 @@ body: | --- name: anyext_v2s64_from_v2s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true legalized: true regBankSelected: true @@ -248,7 +248,7 @@ body: | --- name: zext_v8s16_from_v8s8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -275,7 +275,7 @@ body: | --- name: zext_v4s32_from_v4s16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -301,7 +301,7 @@ body: | --- name: zext_v2s64_from_v2s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -422,7 +422,7 @@ body: | --- name: sext_v8s16_from_v8s8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -449,7 +449,7 @@ body: | --- name: sext_v4s32_from_v4s16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -475,7 +475,7 @@ body: | --- name: sext_v2s64_from_v2s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir index 4efec65d915..3745e4a942d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir @@ -4,7 +4,7 @@ ... --- name: test_f64.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -27,7 +27,7 @@ body: | ... --- name: test_f32.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -50,7 +50,7 @@ body: | ... --- name: test_f16.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -75,7 +75,7 @@ body: | ... --- name: test_v4f16.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -100,7 +100,7 @@ body: | ... --- name: test_v8f16.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -125,7 +125,7 @@ body: | ... --- name: test_v2f32.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -150,7 +150,7 @@ body: | ... --- name: test_v4f32.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -175,7 +175,7 @@ body: | ... --- name: test_v2f64.intrinsic_round -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir index 14926481315..dd9aa187328 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir @@ -4,7 +4,7 @@ ... --- name: test_f64.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -27,7 +27,7 @@ body: | ... --- name: test_f32.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -50,7 +50,7 @@ body: | ... --- name: test_f16.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -75,7 +75,7 @@ body: | ... --- name: test_v4f16.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -100,7 +100,7 @@ body: | ... --- name: test_v8f16.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -125,7 +125,7 @@ body: | ... --- name: test_v2f32.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -150,7 +150,7 @@ body: | ... --- name: test_v4f32.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -175,7 +175,7 @@ body: | ... --- name: test_v2f64.intrinsic_trunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir index 8098fe34269..dfc01fda664 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir @@ -30,7 +30,7 @@ ... --- name: jt_test -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir index 0453bb7fa6e..e6550647524 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir @@ -10,7 +10,7 @@ --- name: test_load_acquire_i8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -32,7 +32,7 @@ body: | ... --- name: test_load_acquire_i16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: test_load_acquire_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -76,7 +76,7 @@ body: | ... --- name: test_load_acquire_i64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir index 167cfc84e2a..13deedddc84 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir @@ -9,7 +9,7 @@ ... --- name: test_load_i8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -31,7 +31,7 @@ body: | ... --- name: test_load_i16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -53,7 +53,7 @@ body: | ... --- name: test_load_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -76,7 +76,7 @@ body: | ... --- name: test_load_i64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir index 5802c6226dc..d46102a6ac8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir @@ -17,7 +17,7 @@ ... --- name: store_v2p0 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -45,7 +45,7 @@ body: | ... --- name: load_v2p0 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir index f7077d67d08..f0b89271a98 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir @@ -536,7 +536,7 @@ body: | ... --- name: load_4xi16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -562,7 +562,7 @@ body: | ... --- name: load_4xi32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -588,7 +588,7 @@ body: | ... --- name: load_8xi16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -614,7 +614,7 @@ body: | ... --- name: load_16xi8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir index a0716b430cf..546be708db8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir @@ -4,7 +4,7 @@ ... --- name: test_v4f16.nearbyint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -27,7 +27,7 @@ body: | ... --- name: test_v8f16.nearbyint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -50,7 +50,7 @@ body: | ... --- name: test_v2f32.nearbyint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -73,7 +73,7 @@ body: | ... --- name: test_v2f64.nearbyint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -96,7 +96,7 @@ body: | ... --- name: test_f32.nearbyint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -119,7 +119,7 @@ body: | ... --- name: test_f64.nearbyint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -142,7 +142,7 @@ body: | ... --- name: test_f16.nearbyint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir index 832a57e7039..5125d9e157d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir @@ -31,7 +31,7 @@ ... --- name: test_phi -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -84,7 +84,7 @@ body: | --- name: test_phi_ptr -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir index 46e0fd41019..4e304f0541c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir @@ -11,7 +11,7 @@ ... --- name: main -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir index e3acf2915b2..c3a56c42a09 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir @@ -4,7 +4,7 @@ ... --- name: select_f32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -36,7 +36,7 @@ body: | ... --- name: select_f64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir index aeb618d0c46..c66d334d16b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir @@ -30,7 +30,7 @@ ... --- name: shuffle_v2f32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -68,7 +68,7 @@ body: | ... --- name: shuffle_v4i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -99,7 +99,7 @@ body: | ... --- name: shuffle_tbl_v4i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -130,7 +130,7 @@ body: | ... --- name: shuffle_v2i64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir index b3836579893..6e01723f499 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir @@ -6,7 +6,7 @@ ... --- name: shuffle_undef_mask_elt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir index 774d156e2b1..c7644ba5d62 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir @@ -15,7 +15,7 @@ ... --- name: test_store_release_i64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -39,7 +39,7 @@ body: | ... --- name: test_store_release_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -63,7 +63,7 @@ body: | ... --- name: test_store_release_i8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -93,7 +93,7 @@ body: | ... --- name: test_store_release_i16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir index 55a3fd8df21..5926d3b2fee 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir @@ -448,7 +448,7 @@ body: | ... --- name: store_4xi16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -474,7 +474,7 @@ body: | ... --- name: store_4xi32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -500,7 +500,7 @@ body: | ... --- name: store_8xi16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -526,7 +526,7 @@ body: | ... --- name: store_16xi8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir index d24f8fa3d13..5e665510623 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir @@ -9,7 +9,7 @@ ... --- name: test_store_i8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -40,7 +40,7 @@ body: | ... --- name: test_store_i16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -71,7 +71,7 @@ body: | ... --- name: test_store_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -97,7 +97,7 @@ body: | ... --- name: test_store_i64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir index 2af588130e9..ad66fa5623e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir @@ -17,7 +17,7 @@ ... --- name: foo -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir index 6012bbe1fd6..96f9ad2b063 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir @@ -4,7 +4,7 @@ ... --- name: uaddo_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -33,7 +33,7 @@ body: | ... --- name: uaddo_s64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir index 5162fa2a543..9565a379677 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir @@ -32,7 +32,7 @@ ... --- name: test_v2s64_unmerge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -58,7 +58,7 @@ body: | ... --- name: test_v4s32_unmerge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -88,7 +88,7 @@ body: | ... --- name: test_v4s16_unmerge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -126,7 +126,7 @@ body: | ... --- name: test_v8s16_unmerge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -164,7 +164,7 @@ body: | ... --- name: test_vecsplit_2v2s32_v4s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -187,7 +187,7 @@ body: | ... --- name: test_vecsplit_2v2s16_v4s16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -212,7 +212,7 @@ body: | ... --- name: test_s128 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir index 9a18c2d6acb..f2273494633 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir @@ -410,7 +410,7 @@ ... --- name: test_v2i64_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -443,7 +443,7 @@ body: | ... --- name: test_v4i32_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -476,7 +476,7 @@ body: | ... --- name: test_v2i32_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -508,7 +508,7 @@ body: | ... --- name: test_v2i16_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -571,7 +571,7 @@ body: | ... --- name: test_v8i16_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -604,7 +604,7 @@ body: | ... --- name: test_v4i16_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -636,7 +636,7 @@ body: | ... --- name: test_v16i8_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -668,7 +668,7 @@ body: | ... --- name: test_v8i8_eq -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -700,7 +700,7 @@ body: | ... --- name: test_v2i64_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -734,7 +734,7 @@ body: | ... --- name: test_v4i32_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -768,7 +768,7 @@ body: | ... --- name: test_v2i32_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -801,7 +801,7 @@ body: | ... --- name: test_v2i16_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -865,7 +865,7 @@ body: | ... --- name: test_v8i16_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -899,7 +899,7 @@ body: | ... --- name: test_v4i16_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -932,7 +932,7 @@ body: | ... --- name: test_v16i8_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -965,7 +965,7 @@ body: | ... --- name: test_v8i8_ne -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -998,7 +998,7 @@ body: | ... --- name: test_v2i64_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1031,7 +1031,7 @@ body: | ... --- name: test_v4i32_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1064,7 +1064,7 @@ body: | ... --- name: test_v2i32_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1096,7 +1096,7 @@ body: | ... --- name: test_v2i16_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1159,7 +1159,7 @@ body: | ... --- name: test_v8i16_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1192,7 +1192,7 @@ body: | ... --- name: test_v4i16_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1224,7 +1224,7 @@ body: | ... --- name: test_v16i8_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1256,7 +1256,7 @@ body: | ... --- name: test_v8i8_ugt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1288,7 +1288,7 @@ body: | ... --- name: test_v2i64_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1321,7 +1321,7 @@ body: | ... --- name: test_v4i32_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1354,7 +1354,7 @@ body: | ... --- name: test_v2i32_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1386,7 +1386,7 @@ body: | ... --- name: test_v2i16_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1449,7 +1449,7 @@ body: | ... --- name: test_v8i16_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1482,7 +1482,7 @@ body: | ... --- name: test_v4i16_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1514,7 +1514,7 @@ body: | ... --- name: test_v16i8_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1546,7 +1546,7 @@ body: | ... --- name: test_v8i8_uge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1578,7 +1578,7 @@ body: | ... --- name: test_v2i64_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1611,7 +1611,7 @@ body: | ... --- name: test_v4i32_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1644,7 +1644,7 @@ body: | ... --- name: test_v2i32_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1676,7 +1676,7 @@ body: | ... --- name: test_v2i16_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1739,7 +1739,7 @@ body: | ... --- name: test_v8i16_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1772,7 +1772,7 @@ body: | ... --- name: test_v4i16_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1804,7 +1804,7 @@ body: | ... --- name: test_v16i8_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1836,7 +1836,7 @@ body: | ... --- name: test_v8i8_ult -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1868,7 +1868,7 @@ body: | ... --- name: test_v2i64_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1901,7 +1901,7 @@ body: | ... --- name: test_v4i32_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1934,7 +1934,7 @@ body: | ... --- name: test_v2i32_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1966,7 +1966,7 @@ body: | ... --- name: test_v2i16_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2029,7 +2029,7 @@ body: | ... --- name: test_v8i16_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2062,7 +2062,7 @@ body: | ... --- name: test_v4i16_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2094,7 +2094,7 @@ body: | ... --- name: test_v16i8_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2126,7 +2126,7 @@ body: | ... --- name: test_v8i8_ule -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2158,7 +2158,7 @@ body: | ... --- name: test_v2i64_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2191,7 +2191,7 @@ body: | ... --- name: test_v4i32_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2224,7 +2224,7 @@ body: | ... --- name: test_v2i32_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2256,7 +2256,7 @@ body: | ... --- name: test_v2i16_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2327,7 +2327,7 @@ body: | ... --- name: test_v8i16_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2360,7 +2360,7 @@ body: | ... --- name: test_v4i16_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2392,7 +2392,7 @@ body: | ... --- name: test_v16i8_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2424,7 +2424,7 @@ body: | ... --- name: test_v8i8_sgt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2456,7 +2456,7 @@ body: | ... --- name: test_v2i64_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2489,7 +2489,7 @@ body: | ... --- name: test_v4i32_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2522,7 +2522,7 @@ body: | ... --- name: test_v2i32_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2554,7 +2554,7 @@ body: | ... --- name: test_v2i16_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2625,7 +2625,7 @@ body: | ... --- name: test_v8i16_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2658,7 +2658,7 @@ body: | ... --- name: test_v4i16_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2690,7 +2690,7 @@ body: | ... --- name: test_v16i8_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2722,7 +2722,7 @@ body: | ... --- name: test_v8i8_sge -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2754,7 +2754,7 @@ body: | ... --- name: test_v2i64_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2787,7 +2787,7 @@ body: | ... --- name: test_v4i32_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2820,7 +2820,7 @@ body: | ... --- name: test_v2i32_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2852,7 +2852,7 @@ body: | ... --- name: test_v2i16_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2923,7 +2923,7 @@ body: | ... --- name: test_v8i16_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2956,7 +2956,7 @@ body: | ... --- name: test_v4i16_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2988,7 +2988,7 @@ body: | ... --- name: test_v16i8_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3020,7 +3020,7 @@ body: | ... --- name: test_v8i8_slt -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3052,7 +3052,7 @@ body: | ... --- name: test_v2i64_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3085,7 +3085,7 @@ body: | ... --- name: test_v4i32_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3118,7 +3118,7 @@ body: | ... --- name: test_v2i32_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3150,7 +3150,7 @@ body: | ... --- name: test_v2i16_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3221,7 +3221,7 @@ body: | ... --- name: test_v8i16_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3254,7 +3254,7 @@ body: | ... --- name: test_v4i16_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3286,7 +3286,7 @@ body: | ... --- name: test_v16i8_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3318,7 +3318,7 @@ body: | ... --- name: test_v8i8_sle -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir index a0033d9661b..95da841e71d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir @@ -2,7 +2,7 @@ # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- name: shl_v2i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -31,7 +31,7 @@ body: | ... --- name: shl_v4i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -60,7 +60,7 @@ body: | ... --- name: ashr_v2i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -90,7 +90,7 @@ body: | ... --- name: ashr_v4i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir index 407f4bff300..587b519554a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir @@ -4,7 +4,7 @@ # RUN: -o - | FileCheck %s --- name: test_rule14_id188_at_idx1067 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -30,7 +30,7 @@ body: | ... --- name: test_rule21_id2237_at_idx1449 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -59,7 +59,7 @@ body: | ... --- name: test_rule22_id2238_at_idx1505 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -88,7 +88,7 @@ body: | ... --- name: test_rule27_id2243_at_idx1781 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -117,7 +117,7 @@ body: | ... --- name: test_rule28_id2244_at_idx1837 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -146,7 +146,7 @@ body: | ... --- name: test_rule29_id2245_at_idx1893 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -175,7 +175,7 @@ body: | ... --- name: test_rule30_id2246_at_idx1949 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -204,7 +204,7 @@ body: | ... --- name: test_rule34_id2250_at_idx2173 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -234,7 +234,7 @@ body: | # The rules that generated this test has changed. The generator should be rerun --- name: test_rule92_id2150_at_idx7770 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -261,7 +261,7 @@ body: | # The rules that generated this test has changed. The generator should be rerun --- name: test_rule96_id2146_at_idx8070 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -290,7 +290,7 @@ body: | ... --- name: test_rule129_id2130_at_idx10828 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -316,7 +316,7 @@ body: | ... --- name: test_rule130_id2131_at_idx10884 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -342,7 +342,7 @@ body: | ... --- name: test_rule135_id2136_at_idx11160 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -368,7 +368,7 @@ body: | ... --- name: test_rule136_id2137_at_idx11216 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -394,7 +394,7 @@ body: | ... --- name: test_rule137_id2138_at_idx11272 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -420,7 +420,7 @@ body: | ... --- name: test_rule138_id2139_at_idx11328 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -446,7 +446,7 @@ body: | ... --- name: test_rule339_id2369_at_idx26608 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -483,7 +483,7 @@ body: | ... --- name: test_rule340_id2370_at_idx26714 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -520,7 +520,7 @@ body: | ... --- name: test_rule341_id2371_at_idx26820 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -557,7 +557,7 @@ body: | ... --- name: test_rule342_id2372_at_idx26926 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -594,7 +594,7 @@ body: | ... --- name: test_rule343_id1266_at_idx27032 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -627,7 +627,7 @@ body: | ... --- name: test_rule344_id1268_at_idx27128 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -660,7 +660,7 @@ body: | ... --- name: test_rule345_id1270_at_idx27224 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -693,7 +693,7 @@ body: | ... --- name: test_rule346_id1326_at_idx27320 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -726,7 +726,7 @@ body: | ... --- name: test_rule347_id1328_at_idx27416 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -759,7 +759,7 @@ body: | ... --- name: test_rule348_id1330_at_idx27512 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -792,7 +792,7 @@ body: | ... --- name: test_rule349_id1308_at_idx27608 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -825,7 +825,7 @@ body: | ... --- name: test_rule350_id1310_at_idx27704 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -858,7 +858,7 @@ body: | ... --- name: test_rule351_id1312_at_idx27800 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -891,7 +891,7 @@ body: | ... --- name: test_rule352_id1356_at_idx27896 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -924,7 +924,7 @@ body: | ... --- name: test_rule353_id1358_at_idx27992 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -957,7 +957,7 @@ body: | ... --- name: test_rule354_id1360_at_idx28088 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -990,7 +990,7 @@ body: | ... --- name: test_rule928_id2367_at_idx60019 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1025,7 +1025,7 @@ body: | ... --- name: test_rule929_id2368_at_idx60105 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1060,7 +1060,7 @@ body: | ... --- name: test_rule930_id2446_at_idx60191 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1095,7 +1095,7 @@ body: | ... --- name: test_rule931_id2447_at_idx60277 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1130,7 +1130,7 @@ body: | ... --- name: test_rule932_id2448_at_idx60363 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1165,7 +1165,7 @@ body: | ... --- name: test_rule934_id429_at_idx60537 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1200,7 +1200,7 @@ body: | ... --- name: test_rule935_id430_at_idx60625 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1235,7 +1235,7 @@ body: | ... --- name: test_rule938_id899_at_idx60889 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1270,7 +1270,7 @@ body: | ... --- name: test_rule939_id900_at_idx60977 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1305,7 +1305,7 @@ body: | ... --- name: test_rule940_id901_at_idx61065 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1340,7 +1340,7 @@ body: | ... --- name: test_rule942_id435_at_idx61241 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1375,7 +1375,7 @@ body: | ... --- name: test_rule943_id436_at_idx61329 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1410,7 +1410,7 @@ body: | ... --- name: test_rule944_id3803_at_idx61417 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1445,7 +1445,7 @@ body: | ... --- name: test_rule945_id3804_at_idx61505 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1480,7 +1480,7 @@ body: | ... --- name: test_rule946_id3805_at_idx61593 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1515,7 +1515,7 @@ body: | ... --- name: test_rule947_id3806_at_idx61681 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1550,7 +1550,7 @@ body: | ... --- name: test_rule950_id3869_at_idx61945 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1581,7 +1581,7 @@ body: | ... --- name: test_rule951_id3871_at_idx62021 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1612,7 +1612,7 @@ body: | ... --- name: test_rule952_id3873_at_idx62097 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1643,7 +1643,7 @@ body: | ... --- name: test_rule953_id3887_at_idx62173 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1674,7 +1674,7 @@ body: | ... --- name: test_rule954_id3889_at_idx62249 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1705,7 +1705,7 @@ body: | ... --- name: test_rule955_id3891_at_idx62325 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1736,7 +1736,7 @@ body: | ... --- name: test_rule956_id927_at_idx62401 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1771,7 +1771,7 @@ body: | ... --- name: test_rule957_id928_at_idx62489 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1806,7 +1806,7 @@ body: | ... --- name: test_rule958_id929_at_idx62577 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1841,7 +1841,7 @@ body: | ... --- name: test_rule959_id930_at_idx62665 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1876,7 +1876,7 @@ body: | ... --- name: test_rule962_id1272_at_idx62929 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1907,7 +1907,7 @@ body: | ... --- name: test_rule963_id1274_at_idx63005 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1938,7 +1938,7 @@ body: | ... --- name: test_rule964_id1276_at_idx63081 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1969,7 +1969,7 @@ body: | ... --- name: test_rule965_id1332_at_idx63157 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2000,7 +2000,7 @@ body: | ... --- name: test_rule966_id1334_at_idx63233 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2031,7 +2031,7 @@ body: | ... --- name: test_rule967_id1336_at_idx63309 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2062,7 +2062,7 @@ body: | ... --- name: test_rule977_id933_at_idx64051 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2097,7 +2097,7 @@ body: | ... --- name: test_rule978_id934_at_idx64139 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2132,7 +2132,7 @@ body: | ... --- name: test_rule979_id935_at_idx64227 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2167,7 +2167,7 @@ body: | ... --- name: test_rule980_id936_at_idx64315 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2202,7 +2202,7 @@ body: | ... --- name: test_rule983_id1314_at_idx64579 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2233,7 +2233,7 @@ body: | ... --- name: test_rule984_id1316_at_idx64655 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2264,7 +2264,7 @@ body: | ... --- name: test_rule985_id1318_at_idx64731 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2295,7 +2295,7 @@ body: | ... --- name: test_rule986_id1362_at_idx64807 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2326,7 +2326,7 @@ body: | ... --- name: test_rule987_id1364_at_idx64883 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2357,7 +2357,7 @@ body: | ... --- name: test_rule988_id1366_at_idx64959 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2388,7 +2388,7 @@ body: | ... --- name: test_rule990_id432_at_idx65123 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2423,7 +2423,7 @@ body: | ... --- name: test_rule991_id433_at_idx65211 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2458,7 +2458,7 @@ body: | ... --- name: test_rule993_id420_at_idx65375 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2489,7 +2489,7 @@ body: | ... --- name: test_rule994_id421_at_idx65451 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2520,7 +2520,7 @@ body: | ... --- name: test_rule1230_id2969_at_idx81784 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2549,7 +2549,7 @@ body: | ... --- name: test_rule1231_id2970_at_idx81816 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2578,7 +2578,7 @@ body: | ... --- name: test_rule1239_id894_at_idx82201 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2611,7 +2611,7 @@ body: | ... --- name: test_rule1240_id895_at_idx82269 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2644,7 +2644,7 @@ body: | ... --- name: test_rule1241_id896_at_idx82337 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2677,7 +2677,7 @@ body: | ... --- name: test_rule1244_id751_at_idx82487 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2706,7 +2706,7 @@ body: | ... --- name: test_rule1245_id752_at_idx82530 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2735,7 +2735,7 @@ body: | ... --- name: test_rule1246_id753_at_idx82573 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2764,7 +2764,7 @@ body: | ... --- name: test_rule1247_id754_at_idx82616 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2793,7 +2793,7 @@ body: | ... --- name: test_rule1254_id1162_at_idx82913 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2822,7 +2822,7 @@ body: | ... --- name: test_rule1255_id1163_at_idx82956 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2851,7 +2851,7 @@ body: | ... --- name: test_rule1256_id1751_at_idx82999 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2880,7 +2880,7 @@ body: | ... --- name: test_rule1259_id1754_at_idx83128 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2909,7 +2909,7 @@ body: | ... --- name: test_rule1268_id829_at_idx83513 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2938,7 +2938,7 @@ body: | ... --- name: test_rule1269_id830_at_idx83556 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2967,7 +2967,7 @@ body: | ... --- name: test_rule1270_id831_at_idx83599 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -2996,7 +2996,7 @@ body: | ... --- name: test_rule1276_id849_at_idx83857 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3025,7 +3025,7 @@ body: | ... --- name: test_rule1277_id850_at_idx83900 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3054,7 +3054,7 @@ body: | ... --- name: test_rule1278_id851_at_idx83943 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3083,7 +3083,7 @@ body: | ... --- name: test_rule1284_id909_at_idx84201 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3112,7 +3112,7 @@ body: | ... --- name: test_rule1285_id910_at_idx84244 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3141,7 +3141,7 @@ body: | ... --- name: test_rule1286_id911_at_idx84287 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3170,7 +3170,7 @@ body: | ... --- name: test_rule1292_id924_at_idx84545 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3199,7 +3199,7 @@ body: | ... --- name: test_rule1293_id925_at_idx84588 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3228,7 +3228,7 @@ body: | ... --- name: test_rule1294_id926_at_idx84631 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3257,7 +3257,7 @@ body: | ... --- name: test_rule1296_id939_at_idx84715 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3286,7 +3286,7 @@ body: | ... --- name: test_rule1297_id940_at_idx84758 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3315,7 +3315,7 @@ body: | ... --- name: test_rule1298_id941_at_idx84801 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3344,7 +3344,7 @@ body: | ... --- name: test_rule1299_id942_at_idx84844 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3373,7 +3373,7 @@ body: | ... --- name: test_rule1304_id1174_at_idx85055 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3402,7 +3402,7 @@ body: | ... --- name: test_rule1305_id1175_at_idx85098 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3431,7 +3431,7 @@ body: | ... --- name: test_rule1306_id1827_at_idx85141 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3460,7 +3460,7 @@ body: | ... --- name: test_rule1309_id1830_at_idx85270 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3489,7 +3489,7 @@ body: | ... --- name: test_rule1315_id1051_at_idx85522 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3518,7 +3518,7 @@ body: | ... --- name: test_rule1316_id1052_at_idx85565 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3547,7 +3547,7 @@ body: | ... --- name: test_rule1317_id1053_at_idx85608 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3576,7 +3576,7 @@ body: | ... --- name: test_rule1318_id1054_at_idx85651 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3605,7 +3605,7 @@ body: | ... --- name: test_rule1329_id1170_at_idx86118 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3634,7 +3634,7 @@ body: | ... --- name: test_rule1330_id1171_at_idx86161 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3663,7 +3663,7 @@ body: | ... --- name: test_rule1331_id1791_at_idx86204 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3692,7 +3692,7 @@ body: | ... --- name: test_rule1334_id1794_at_idx86333 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3721,7 +3721,7 @@ body: | ... --- name: test_rule1337_id2925_at_idx86462 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3746,7 +3746,7 @@ body: | ... --- name: test_rule1338_id2928_at_idx86507 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3771,7 +3771,7 @@ body: | ... --- name: test_rule1339_id2931_at_idx86552 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3796,7 +3796,7 @@ body: | ... --- name: test_rule1582_id372_at_idx97075 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3821,7 +3821,7 @@ body: | ... --- name: test_rule1583_id373_at_idx97110 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3846,7 +3846,7 @@ body: | ... --- name: test_rule1586_id597_at_idx97215 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3871,7 +3871,7 @@ body: | ... --- name: test_rule1587_id598_at_idx97250 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3896,7 +3896,7 @@ body: | ... --- name: test_rule1588_id599_at_idx97285 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3921,7 +3921,7 @@ body: | ... --- name: test_rule1592_id2383_at_idx97425 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3946,7 +3946,7 @@ body: | ... --- name: test_rule1593_id2385_at_idx97458 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3971,7 +3971,7 @@ body: | ... --- name: test_rule1602_id587_at_idx97771 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -3996,7 +3996,7 @@ body: | ... --- name: test_rule1603_id588_at_idx97806 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4021,7 +4021,7 @@ body: | ... --- name: test_rule1604_id589_at_idx97841 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4046,7 +4046,7 @@ body: | ... --- name: test_rule1613_id592_at_idx98156 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4071,7 +4071,7 @@ body: | ... --- name: test_rule1614_id593_at_idx98191 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4096,7 +4096,7 @@ body: | ... --- name: test_rule1615_id594_at_idx98226 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4121,7 +4121,7 @@ body: | ... --- name: test_rule1619_id2389_at_idx98366 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4146,7 +4146,7 @@ body: | ... --- name: test_rule1620_id2390_at_idx98399 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4171,7 +4171,7 @@ body: | ... --- name: test_rule1621_id2923_at_idx98432 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4196,7 +4196,7 @@ body: | ... --- name: test_rule1622_id2926_at_idx98477 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4221,7 +4221,7 @@ body: | ... --- name: test_rule1623_id2929_at_idx98522 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4246,7 +4246,7 @@ body: | ... --- name: test_rule1632_id687_at_idx98847 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4271,7 +4271,7 @@ body: | ... --- name: test_rule1633_id688_at_idx98882 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4296,7 +4296,7 @@ body: | ... --- name: test_rule1634_id689_at_idx98917 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4321,7 +4321,7 @@ body: | ... --- name: test_rule1635_id748_at_idx98952 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4346,7 +4346,7 @@ body: | ... --- name: test_rule1636_id749_at_idx98987 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4371,7 +4371,7 @@ body: | ... --- name: test_rule1637_id750_at_idx99022 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4396,7 +4396,7 @@ body: | ... --- name: test_rule1647_id731_at_idx99386 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4421,7 +4421,7 @@ body: | ... --- name: test_rule1648_id732_at_idx99421 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4446,7 +4446,7 @@ body: | ... --- name: test_rule1649_id733_at_idx99456 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4471,7 +4471,7 @@ body: | ... --- name: test_rule1650_id2924_at_idx99491 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4496,7 +4496,7 @@ body: | ... --- name: test_rule1651_id2927_at_idx99536 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -4521,7 +4521,7 @@ body: | ... --- name: test_rule1652_id2930_at_idx99581 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir index 53d73975dde..f86c7e4793f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir @@ -13,7 +13,7 @@ --- name: strxrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -35,7 +35,7 @@ body: | ... --- name: strdrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -57,7 +57,7 @@ body: | ... --- name: strwrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -79,7 +79,7 @@ body: | ... --- name: strsrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -101,7 +101,7 @@ body: | ... --- name: strhrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -123,7 +123,7 @@ body: | ... --- name: strqrox -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -145,7 +145,7 @@ body: | ... --- name: shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir index b90bf635c1a..f7f5d260f44 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir @@ -128,7 +128,7 @@ ... --- name: main -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir b/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir index a29e9e5a405..10d311253c6 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir @@ -65,7 +65,7 @@ body: | ... --- name: test_q10_q11_x19_x20 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0.entry: diff --git a/llvm/test/CodeGen/AArch64/branch-relax-block-size.mir b/llvm/test/CodeGen/AArch64/branch-relax-block-size.mir index 5632d279496..661bdf2d1bc 100644 --- a/llvm/test/CodeGen/AArch64/branch-relax-block-size.mir +++ b/llvm/test/CodeGen/AArch64/branch-relax-block-size.mir @@ -35,7 +35,7 @@ ... --- name: test -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$x0' } diff --git a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir index 3a35388829a..0755e3b4c3b 100644 --- a/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir +++ b/llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir @@ -116,7 +116,7 @@ ... --- name: compiler_pop_stack -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$w0' } @@ -174,7 +174,7 @@ body: | ... --- name: f -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$x0' } diff --git a/llvm/test/CodeGen/AArch64/irg-nomem.mir b/llvm/test/CodeGen/AArch64/irg-nomem.mir index 40ac76b5e37..d023fd6405b 100644 --- a/llvm/test/CodeGen/AArch64/irg-nomem.mir +++ b/llvm/test/CodeGen/AArch64/irg-nomem.mir @@ -19,7 +19,7 @@ ... --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/jump-table-compress.mir b/llvm/test/CodeGen/AArch64/jump-table-compress.mir index b4217ea6168..fd322993b8b 100644 --- a/llvm/test/CodeGen/AArch64/jump-table-compress.mir +++ b/llvm/test/CodeGen/AArch64/jump-table-compress.mir @@ -7,7 +7,7 @@ ... --- name: test_jumptable -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-inline-asm-adrp.mir b/llvm/test/CodeGen/AArch64/machine-outliner-inline-asm-adrp.mir index 4992c1a247a..5c54ce2ea1c 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-inline-asm-adrp.mir +++ b/llvm/test/CodeGen/AArch64/machine-outliner-inline-asm-adrp.mir @@ -22,7 +22,7 @@ ... --- name: foo -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0 (%ir-block.0): @@ -34,7 +34,7 @@ body: | ... --- name: foo2 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0 (%ir-block.0): @@ -46,7 +46,7 @@ body: | ... --- name: foo3 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0 (%ir-block.0): diff --git a/llvm/test/CodeGen/AArch64/movimm-wzr.mir b/llvm/test/CodeGen/AArch64/movimm-wzr.mir index 50405c79973..cbcede87f77 100644 --- a/llvm/test/CodeGen/AArch64/movimm-wzr.mir +++ b/llvm/test/CodeGen/AArch64/movimm-wzr.mir @@ -13,7 +13,7 @@ ... --- name: test_mov_0 -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: false frameInfo: diff --git a/llvm/test/CodeGen/AArch64/reverse-csr-restore-seq.mir b/llvm/test/CodeGen/AArch64/reverse-csr-restore-seq.mir index 327ce9e5359..a2c9a25da24 100644 --- a/llvm/test/CodeGen/AArch64/reverse-csr-restore-seq.mir +++ b/llvm/test/CodeGen/AArch64/reverse-csr-restore-seq.mir @@ -78,7 +78,7 @@ body: | # false. name: baz # CHECK-LABEL: name: baz -alignment: 2 +alignment: 4 tracksRegLiveness: true frameInfo: adjustsStack: true diff --git a/llvm/test/CodeGen/AArch64/spill-undef.mir b/llvm/test/CodeGen/AArch64/spill-undef.mir index 9fb0c44ac0d..86cf83df54b 100644 --- a/llvm/test/CodeGen/AArch64/spill-undef.mir +++ b/llvm/test/CodeGen/AArch64/spill-undef.mir @@ -15,7 +15,7 @@ ... --- name: foobar -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gpr32 } diff --git a/llvm/test/CodeGen/AArch64/wineh-frame0.mir b/llvm/test/CodeGen/AArch64/wineh-frame0.mir index b59627d7f31..c7e9e19fca1 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame0.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame0.mir @@ -30,7 +30,7 @@ ... --- name: test -alignment: 2 +alignment: 4 tracksRegLiveness: true hasWinCFI: true liveins: diff --git a/llvm/test/CodeGen/AArch64/wineh-frame1.mir b/llvm/test/CodeGen/AArch64/wineh-frame1.mir index deff40160b2..3604f610c95 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame1.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame1.mir @@ -37,7 +37,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh-frame2.mir b/llvm/test/CodeGen/AArch64/wineh-frame2.mir index ae2aaf7f27d..be7598ce494 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame2.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame2.mir @@ -25,7 +25,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh-frame3.mir b/llvm/test/CodeGen/AArch64/wineh-frame3.mir index d6e927d4bd5..542192e1149 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame3.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame3.mir @@ -17,7 +17,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh-frame4.mir b/llvm/test/CodeGen/AArch64/wineh-frame4.mir index 63a8dc67779..0f525450908 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame4.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame4.mir @@ -17,7 +17,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh-frame5.mir b/llvm/test/CodeGen/AArch64/wineh-frame5.mir index 98897bf67a7..c69ac3dd5d8 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame5.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame5.mir @@ -68,7 +68,7 @@ ... --- name: '?func@@YAHH@Z' -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh-frame6.mir b/llvm/test/CodeGen/AArch64/wineh-frame6.mir index e61e016aa51..975fba11715 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame6.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame6.mir @@ -55,7 +55,7 @@ ... --- name: '?func@@YAHHHHH@Z' -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh-frame7.mir b/llvm/test/CodeGen/AArch64/wineh-frame7.mir index 11591d3e367..3d4d4be67bc 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame7.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame7.mir @@ -74,7 +74,7 @@ ... --- name: '?func@@YAHH@Z' -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AArch64/wineh-frame8.mir b/llvm/test/CodeGen/AArch64/wineh-frame8.mir index 3d50fcf7fc6..69de391930e 100644 --- a/llvm/test/CodeGen/AArch64/wineh-frame8.mir +++ b/llvm/test/CodeGen/AArch64/wineh-frame8.mir @@ -34,7 +34,7 @@ ... --- name: '?func@@YAHH@Z' -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AArch64/wineh1.mir b/llvm/test/CodeGen/AArch64/wineh1.mir index 1ffaa25d30d..e468d7f0b82 100644 --- a/llvm/test/CodeGen/AArch64/wineh1.mir +++ b/llvm/test/CodeGen/AArch64/wineh1.mir @@ -50,7 +50,7 @@ ... --- name: test -alignment: 2 +alignment: 4 tracksRegLiveness: true hasWinCFI: true liveins: diff --git a/llvm/test/CodeGen/AArch64/wineh2.mir b/llvm/test/CodeGen/AArch64/wineh2.mir index 05a232f753f..aa78ee7b93b 100644 --- a/llvm/test/CodeGen/AArch64/wineh2.mir +++ b/llvm/test/CodeGen/AArch64/wineh2.mir @@ -43,7 +43,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh3.mir b/llvm/test/CodeGen/AArch64/wineh3.mir index f2aea13d2a1..82f65eac457 100644 --- a/llvm/test/CodeGen/AArch64/wineh3.mir +++ b/llvm/test/CodeGen/AArch64/wineh3.mir @@ -41,7 +41,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh4.mir b/llvm/test/CodeGen/AArch64/wineh4.mir index 6f03a3816a7..185b11178b6 100644 --- a/llvm/test/CodeGen/AArch64/wineh4.mir +++ b/llvm/test/CodeGen/AArch64/wineh4.mir @@ -54,7 +54,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh5.mir b/llvm/test/CodeGen/AArch64/wineh5.mir index 56b8d474ea9..0f4a25a2e43 100644 --- a/llvm/test/CodeGen/AArch64/wineh5.mir +++ b/llvm/test/CodeGen/AArch64/wineh5.mir @@ -89,7 +89,7 @@ ... --- name: '?func@@YAHH@Z' -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AArch64/wineh6.mir b/llvm/test/CodeGen/AArch64/wineh6.mir index 12711ebdde9..bff09cba626 100644 --- a/llvm/test/CodeGen/AArch64/wineh6.mir +++ b/llvm/test/CodeGen/AArch64/wineh6.mir @@ -30,7 +30,7 @@ ... --- name: '?func@@YAHHHHH@Z' -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh7.mir b/llvm/test/CodeGen/AArch64/wineh7.mir index 2d1b19a927c..040ab61f916 100644 --- a/llvm/test/CodeGen/AArch64/wineh7.mir +++ b/llvm/test/CodeGen/AArch64/wineh7.mir @@ -35,7 +35,7 @@ ... --- name: '?func@@YAHHHHH@Z' -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh8.mir b/llvm/test/CodeGen/AArch64/wineh8.mir index 018412aa97c..f99722adee9 100644 --- a/llvm/test/CodeGen/AArch64/wineh8.mir +++ b/llvm/test/CodeGen/AArch64/wineh8.mir @@ -53,7 +53,7 @@ ... --- name: test -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir b/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir index 6b97a153288..bfdac4e0065 100644 --- a/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir +++ b/llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir @@ -74,7 +74,7 @@ ... --- name: '?func@@YAHHH@Z' -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir index 0a39304d446..72f91e0ffaf 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir @@ -15,7 +15,7 @@ ... --- name: test_blockaddress -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir index 17b1e0982e6..dfff28fc63a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir @@ -16,7 +16,7 @@ ... --- name: test_blockaddress -alignment: 4 +alignment: 16 legalized: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir index 1295a75ed2c..3d1b98714c5 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir @@ -5,7 +5,7 @@ --- name: main -alignment: 0 +alignment: 1 tracksRegLiveness: true registers: - { id: 0, class: sreg_64 } diff --git a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index 49b8b1af7d5..e5ff97a7be3 100644 --- a/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -5,7 +5,7 @@ # GCN: %10:vgpr_32 = V_MOV_B32_e32 1543, implicit $exec # GCN: BUFFER_STORE_DWORD_OFFSET killed %10, name: s_fold_and_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -78,7 +78,7 @@ body: | # GCN: FLAT_STORE_DWORD %19, %13, name: v_fold_and_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -168,7 +168,7 @@ body: | # GCN: BUFFER_STORE_DWORD_OFFSET killed %13, name: s_fold_shl_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -257,7 +257,7 @@ body: | # GCN: FLAT_STORE_DWORD %20, %28, name: v_fold_shl_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -370,7 +370,7 @@ body: | # GCN: %11:vgpr_32 = V_MOV_B32_e32 243, implicit $exec # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8, name: s_fold_ashr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -456,7 +456,7 @@ body: | # GCN: FLAT_STORE_DWORD %20, %28, name: v_fold_ashr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -578,7 +578,7 @@ body: | # GCN: %11:vgpr_32 = V_MOV_B32_e32 1048332, implicit $exec # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8, name: s_fold_lshr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -665,7 +665,7 @@ body: | # GCN: FLAT_STORE_DWORD %20, %28, name: v_fold_lshr_imm_regimm_32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -837,7 +837,7 @@ body: | # GCN-NEXT: S_ENDPGM 0, implicit %2 name: constant_fold_lshl_or_reg0_immreg_reg -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -862,7 +862,7 @@ body: | # GCN-NEXT: S_ENDPGM 0, implicit %2 name: constant_fold_lshl_or_reg0_immreg_imm -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -886,7 +886,7 @@ body: | # GCN-NEXT: S_ENDPGM 0, implicit %3 name: constant_fold_lshl_or_reg0_immreg_immreg -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir index 7d1db87c4b5..4679831c786 100644 --- a/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir +++ b/llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir @@ -150,7 +150,7 @@ ... --- name: _amdgpu_ps_main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir index 66a238dff82..8135de9feba 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir +++ b/llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir @@ -6,7 +6,7 @@ --- name: main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir index e2f6dc1510d..d31a9c97bdb 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir +++ b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir @@ -24,7 +24,7 @@ ... --- name: flat_load_clustering -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir index 8330a07837d..3ab99551012 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir @@ -114,7 +114,7 @@ # CHECK: %13:vgpr_32 = V_ADD_F16_e32 1065353216, killed %11, implicit $exec name: add_f32_1.0_one_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -176,7 +176,7 @@ body: | name: add_f32_1.0_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -242,7 +242,7 @@ body: | # CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec name: add_f32_1.0_one_f32_use_one_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -312,7 +312,7 @@ body: | # CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec name: add_f32_1.0_one_f32_use_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -381,7 +381,7 @@ body: | name: add_i32_1_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -446,7 +446,7 @@ body: | # CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit $exec name: add_i32_m2_one_f32_use_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -518,7 +518,7 @@ body: | # CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit $exec name: add_f16_1.0_multi_f32_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -585,7 +585,7 @@ body: | # CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec name: add_f16_1.0_other_high_bits_multi_f16_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -651,7 +651,7 @@ body: | # CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $exec # CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec name: add_f16_1.0_other_high_bits_use_f16_f32 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/hazard.mir b/llvm/test/CodeGen/AMDGPU/hazard.mir index 80fa69b8d6b..bc62bd9ef08 100644 --- a/llvm/test/CodeGen/AMDGPU/hazard.mir +++ b/llvm/test/CodeGen/AMDGPU/hazard.mir @@ -11,7 +11,7 @@ --- name: hazard_implicit_def -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -40,7 +40,7 @@ body: | # GCN: V_INTERP_P1_F32 --- name: hazard_inlineasm -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir index 6159f646b05..9f39dc34150 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir +++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir @@ -25,7 +25,7 @@ # CHECK: $vgpr2 = V_MOV_B32 # CHECK: $vgpr3 = V_MOV_B32 name: exp_done_waitcnt -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir index c4cc1c24973..6e67f7df30a 100644 --- a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir +++ b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir @@ -514,7 +514,7 @@ body: | ... --- name: mov_fed_hazard_crash_on_dbg_value -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir index b33a6beb6ce..48f0be4ff8f 100644 --- a/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir +++ b/llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir @@ -29,7 +29,7 @@ # CHECK: S_CBRANCH_VCCZ %bb.1, implicit undef $vcc name: invert_br_undef_vcc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir index e698995e435..fbf59da6c2f 100644 --- a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir +++ b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir @@ -16,7 +16,7 @@ --- name: main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir b/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir index eed7e049961..f33c2115dcb 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir @@ -52,7 +52,7 @@ # CHECK-NEXT: BUFFER_WBINVL1_VOL name: atomic_max_i32_noret -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir index 65775e35521..bf24ce15acb 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir @@ -65,7 +65,7 @@ # CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 1, 1, 0, 0 name: multiple_mem_operands -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir index 97f7f74a743..a6088b0677a 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir @@ -45,7 +45,7 @@ # CHECK: BUFFER_LOAD_DWORD_OFFEN killed $vgpr0, killed $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr3, 0, 0, 0, 0, 0 name: multiple_mem_operands -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir index 766b687b758..7a541b20185 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir @@ -25,7 +25,7 @@ ... --- name: scc_def_and_use_no_dependency -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -72,7 +72,7 @@ body: | # CHECK: S_ADDC_U32 --- name: scc_def_and_use_dependency -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir index 0e31eba262f..becd2e1b9c1 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-load-store.mir +++ b/llvm/test/CodeGen/AMDGPU/merge-load-store.mir @@ -70,7 +70,7 @@ ... --- name: mem_dependency -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir index d402ca850d3..3af2f0457fb 100644 --- a/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir @@ -57,7 +57,7 @@ ... --- name: const_to_sgpr -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -146,7 +146,7 @@ body: | ... --- name: const_to_sgpr_multiple_use -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -252,7 +252,7 @@ body: | ... --- name: const_to_sgpr_subreg -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir index 2e737143ed3..0413075dd86 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir @@ -5,7 +5,7 @@ # GCN: undef %18.sub0:vreg_128 = V_MAC_F32_e32 undef %3:vgpr_32, undef %9:vgpr_32, undef %18.sub0, implicit $exec name: mac_invalid_operands -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -91,7 +91,7 @@ body: | # GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0, # GCN: BUFFER_STORE_DWORD_OFFEN %7.sub0, %0, name: vreg_does_not_dominate -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir index 0b995c680f6..eee471cb073 100644 --- a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir +++ b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir @@ -172,7 +172,7 @@ # CHECK: DBG_VALUE %99, $noreg, !5, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !8 name: sched_dbg_value_crash -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir index 3bec72cc538..cd9a909ac7c 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir @@ -10,7 +10,7 @@ --- name: mo_pset -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir b/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir index d6045a0a2d4..2e96d2129ec 100644 --- a/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir +++ b/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir @@ -91,7 +91,7 @@ ... --- name: sdwa_imm_operand -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -252,7 +252,7 @@ body: | ... --- name: sdwa_sgpr_operand -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir index d9147609ddd..2aaf7f10b69 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir +++ b/llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir @@ -11,7 +11,7 @@ # GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, 0, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec name: shrink_add_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -95,7 +95,7 @@ body: | # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec name: shrink_sub_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -179,7 +179,7 @@ body: | # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec name: shrink_subrev_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -262,7 +262,7 @@ body: | # GCN: %29:vgpr_32, $vcc = V_ADDC_U32_e64 %19, %17, %9, 0, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec name: check_addc_src2_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -347,7 +347,7 @@ body: | # GCN %24 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec name: shrink_addc_vop3 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -432,7 +432,7 @@ body: | # GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def $vcc, implicit undef $vcc, implicit $exec # GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed $vcc, implicit $exec name: shrink_addc_undef_vcc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir b/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir index ce4a7f9dd6a..f461b1a1159 100644 --- a/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir +++ b/llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir @@ -9,7 +9,7 @@ --- name: _amdgpu_cs_main -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir index e366a0ebb0e..cda6ecd4650 100644 --- a/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir @@ -22,7 +22,7 @@ # CHECK-NEXT: $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc # CHECK: $exec = COPY killed $sgpr2_sgpr3 name: undefined_physreg_sgpr_spill -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -87,7 +87,7 @@ body: | # CHECK: SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5) # CHECK: $exec = COPY killed $sgpr2_sgpr3 name: undefined_physreg_sgpr_spill_reorder -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir index d0a7c57f333..41444b0ef0c 100644 --- a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir +++ b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir @@ -52,7 +52,7 @@ # CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed $vcc name: vccz_corrupt_workaround -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -114,7 +114,7 @@ body: | # CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 name: vccz_corrupt_undef_vcc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/AMDGPU/wqm.mir b/llvm/test/CodeGen/AMDGPU/wqm.mir index 6531d625866..a5009cc7924 100644 --- a/llvm/test/CodeGen/AMDGPU/wqm.mir +++ b/llvm/test/CodeGen/AMDGPU/wqm.mir @@ -7,7 +7,7 @@ #CHECK: S_CMP_LT_I32 #CHECK: S_CSELECT_B32 name: test_wwm_scc -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir index ce33dcf52ec..bbd7cce5cb2 100644 --- a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -77,7 +77,7 @@ ... --- name: f -alignment: 1 +alignment: 2 exposesReturnsTwice: false tracksRegLiveness: true liveins: diff --git a/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir b/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir index 8ff1847f20e..319ddca358e 100644 --- a/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir +++ b/llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir @@ -18,7 +18,7 @@ --- name: f # CHECK-LABEL: name: f -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir b/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir index c447fede691..ba983ba5bf2 100644 --- a/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir +++ b/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir @@ -37,7 +37,7 @@ --- name: g # CHECK-LABEL: name: g -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/constant-island-movwt.mir b/llvm/test/CodeGen/ARM/constant-island-movwt.mir index 4aac918ad33..418e87abf3d 100644 --- a/llvm/test/CodeGen/ARM/constant-island-movwt.mir +++ b/llvm/test/CodeGen/ARM/constant-island-movwt.mir @@ -315,7 +315,7 @@ ... --- name: func -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/constant-islands-cfg.mir b/llvm/test/CodeGen/ARM/constant-islands-cfg.mir index c83a4ad956e..add9e2003a5 100644 --- a/llvm/test/CodeGen/ARM/constant-islands-cfg.mir +++ b/llvm/test/CodeGen/ARM/constant-islands-cfg.mir @@ -7,7 +7,7 @@ ... --- name: test_split_cfg -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir b/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir index 47b3cd1c43d..7eae259675b 100644 --- a/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir +++ b/llvm/test/CodeGen/ARM/constant-islands-split-IT.mir @@ -21,7 +21,7 @@ ... --- name: h -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/dbg-range-extension.mir b/llvm/test/CodeGen/ARM/dbg-range-extension.mir index 0a48ba83c09..75eb466f7cb 100644 --- a/llvm/test/CodeGen/ARM/dbg-range-extension.mir +++ b/llvm/test/CodeGen/ARM/dbg-range-extension.mir @@ -164,7 +164,7 @@ ... --- name: func -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/expand-pseudos.mir b/llvm/test/CodeGen/ARM/expand-pseudos.mir index e10471fc795..568e96eacb5 100644 --- a/llvm/test/CodeGen/ARM/expand-pseudos.mir +++ b/llvm/test/CodeGen/ARM/expand-pseudos.mir @@ -17,7 +17,7 @@ ... --- name: test1 -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$r0', virtual-reg: '' } @@ -34,7 +34,7 @@ body: | ... --- name: test2 -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$r0', virtual-reg: '' } @@ -51,7 +51,7 @@ body: | ... --- name: test3 -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$r0', virtual-reg: '' } diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir index c893c4ef931..86457a7815c 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir @@ -33,7 +33,7 @@ ... --- name: ARM -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$r0' } diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir b/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir index d2bb9bfefd0..aca33a1e457 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir @@ -35,7 +35,7 @@ ... --- name: THUMB -alignment: 1 +alignment: 2 tracksRegLiveness: true frameInfo: stackSize: 8 diff --git a/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir index 6f40c86ce8e..194ec839b71 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir @@ -38,7 +38,7 @@ ... --- name: CP -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir index 97ddebc426c..abd4a6d7f63 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir @@ -39,7 +39,7 @@ ... --- name: CP -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir b/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir index a2218b149f1..8c179958b01 100644 --- a/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir +++ b/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir @@ -18,7 +18,7 @@ ... --- name: fn1 -alignment: 1 +alignment: 2 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir index 04a6f6b0005..1918e3144ec 100644 --- a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir +++ b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir @@ -100,7 +100,7 @@ ... --- name: foo -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/misched-int-basic.mir b/llvm/test/CodeGen/ARM/misched-int-basic.mir index 41a92831af8..4a52af19424 100644 --- a/llvm/test/CodeGen/ARM/misched-int-basic.mir +++ b/llvm/test/CodeGen/ARM/misched-int-basic.mir @@ -66,7 +66,7 @@ ... --- name: foo -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir b/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir index 67fff944c76..6da3877be23 100644 --- a/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir +++ b/llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir @@ -15,7 +15,7 @@ ... --- name: ldrd_strd_aa -alignment: 1 +alignment: 2 tracksRegLiveness: true liveins: - { reg: '$r0', virtual-reg: '%0' } diff --git a/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir b/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir index c5c463446ad..37d68c57764 100644 --- a/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir +++ b/llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir @@ -17,7 +17,7 @@ --- # CHECK-LABEL: name: a name: a -alignment: 1 +alignment: 2 tracksRegLiveness: true liveins: - { reg: '$r0', virtual-reg: '%0' } @@ -60,7 +60,7 @@ body: | --- # CHECK-LABEL: name: b name: b -alignment: 1 +alignment: 2 tracksRegLiveness: true liveins: - { reg: '$r0', virtual-reg: '%0' } diff --git a/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir index ec42e7df3b2..bbb5caa76e9 100644 --- a/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir +++ b/llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir @@ -88,7 +88,7 @@ ... --- name: f -alignment: 1 +alignment: 2 exposesReturnsTwice: false tracksRegLiveness: true liveins: diff --git a/llvm/test/CodeGen/ARM/single-issue-r52.mir b/llvm/test/CodeGen/ARM/single-issue-r52.mir index 22be6a0eade..ddfe46815cc 100644 --- a/llvm/test/CodeGen/ARM/single-issue-r52.mir +++ b/llvm/test/CodeGen/ARM/single-issue-r52.mir @@ -41,7 +41,7 @@ ... --- name: foo -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir index 0c6204a24c4..a572ce5e1a0 100644 --- a/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir +++ b/llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir @@ -188,7 +188,7 @@ ... --- name: foo -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -286,7 +286,7 @@ body: | --- name: bar -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/ARM/vldm-liveness.mir b/llvm/test/CodeGen/ARM/vldm-liveness.mir index 9f2f45dc109..bc97b99a436 100644 --- a/llvm/test/CodeGen/ARM/vldm-liveness.mir +++ b/llvm/test/CodeGen/ARM/vldm-liveness.mir @@ -19,7 +19,7 @@ ... --- name: foo -alignment: 1 +alignment: 2 liveins: - { reg: '$r0' } body: | diff --git a/llvm/test/CodeGen/ARM/vldmia-sched.mir b/llvm/test/CodeGen/ARM/vldmia-sched.mir index 75ee9335835..30b5d928cc7 100644 --- a/llvm/test/CodeGen/ARM/vldmia-sched.mir +++ b/llvm/test/CodeGen/ARM/vldmia-sched.mir @@ -14,7 +14,7 @@ ... --- name: g -alignment: 1 +alignment: 2 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/Hexagon/bank-conflict.mir b/llvm/test/CodeGen/Hexagon/bank-conflict.mir index fbef6410fa3..ee055f9ac71 100644 --- a/llvm/test/CodeGen/Hexagon/bank-conflict.mir +++ b/llvm/test/CodeGen/Hexagon/bank-conflict.mir @@ -89,7 +89,7 @@ ... --- name: f0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: liveins: diff --git a/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir b/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir index bbb2dce009c..1dd6d36435c 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir @@ -40,7 +40,7 @@ ... --- name: f0 -alignment: 4 +alignment: 16 registers: - { id: 0, class: intregs, preferred-register: '' } - { id: 1, class: intregs, preferred-register: '' } diff --git a/llvm/test/CodeGen/Hexagon/early-if-predicator.mir b/llvm/test/CodeGen/Hexagon/early-if-predicator.mir index e93a49a8ed8..785fcd9d873 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-predicator.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-predicator.mir @@ -21,7 +21,7 @@ ... --- name: if-cvt -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir b/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir index 81febed7430..0db49f36731 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir @@ -20,7 +20,7 @@ --- name: foo -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r0' } diff --git a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir index a5d8c09a6b5..5b953f13b1b 100644 --- a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir +++ b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir @@ -56,7 +56,7 @@ ... --- name: f0 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir index b6522029270..06f3b3a7069 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir @@ -64,7 +64,7 @@ ... --- name: main -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: intregs } diff --git a/llvm/test/CodeGen/Lanai/peephole-compare.mir b/llvm/test/CodeGen/Lanai/peephole-compare.mir index 68409d645ce..61568e451af 100644 --- a/llvm/test/CodeGen/Lanai/peephole-compare.mir +++ b/llvm/test/CodeGen/Lanai/peephole-compare.mir @@ -173,7 +173,7 @@ ... --- name: test0a -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -217,7 +217,7 @@ body: | ... --- name: test0b -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -259,7 +259,7 @@ body: | ... --- name: test1a -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -305,7 +305,7 @@ body: | ... --- name: test1b -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -351,7 +351,7 @@ body: | ... --- name: test2a -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -397,7 +397,7 @@ body: | ... --- name: test2b -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -443,7 +443,7 @@ body: | ... --- name: test3 -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -489,7 +489,7 @@ body: | ... --- name: test4 -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: @@ -599,7 +599,7 @@ body: | ... --- name: testBB -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir index b1913149df0..a4a5533ff2c 100644 --- a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir +++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir @@ -35,7 +35,7 @@ # FALLBACK-LABEL: name: test # FALLBACK-NOT: failedISel name: test -alignment: 2 +alignment: 4 legalized: true regBankSelected: true failedISel: true diff --git a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir index 1489c677567..1feb96a6403 100644 --- a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir +++ b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir @@ -16,7 +16,7 @@ --- #CHECK: foo name: foo -alignment: 2 +alignment: 4 tracksRegLiveness: true frameInfo: maxCallFrameSize: 0 @@ -32,7 +32,7 @@ body: | --- #CHECK: bar name: bar -alignment: 2 +alignment: 4 tracksRegLiveness: true frameInfo: maxCallFrameSize: 0 diff --git a/llvm/test/CodeGen/MIR/AArch64/swp.mir b/llvm/test/CodeGen/MIR/AArch64/swp.mir index 4c39b4aa931..d7555bf8938 100644 --- a/llvm/test/CodeGen/MIR/AArch64/swp.mir +++ b/llvm/test/CodeGen/MIR/AArch64/swp.mir @@ -11,7 +11,7 @@ ... --- name: swp -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gpr64common } diff --git a/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir b/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir index f5a38aff03a..44b45ec31b1 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir @@ -48,7 +48,7 @@ ... --- name: syncscopes -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/MIR/Generic/machine-function.mir b/llvm/test/CodeGen/MIR/Generic/machine-function.mir index 9c19b980e67..14764ec44c7 100644 --- a/llvm/test/CodeGen/MIR/Generic/machine-function.mir +++ b/llvm/test/CodeGen/MIR/Generic/machine-function.mir @@ -36,18 +36,18 @@ name: bar ... --- # CHECK: name: func -# CHECK-NEXT: alignment: 8 +# CHECK-NEXT: alignment: 256 # CHECK-NEXT: exposesReturnsTwice: false # CHECK: ... name: func -alignment: 8 +alignment: 256 ... --- # CHECK: name: func2 -# CHECK-NEXT: alignment: 16 +# CHECK-NEXT: alignment: 65536 # CHECK-NEXT: exposesReturnsTwice: true # CHECK: ... name: func2 -alignment: 16 +alignment: 65536 exposesReturnsTwice: true ... diff --git a/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir b/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir index 76fde05be70..9f50a0709a6 100644 --- a/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir +++ b/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir @@ -3,7 +3,7 @@ # RUN: -simplify-mir %s -o - | FileCheck %s --- name: poc -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | ; CHECK-LABEL: name: poc diff --git a/llvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir b/llvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir index 15ff4dd4834..59df0e1cf60 100644 --- a/llvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir +++ b/llvm/test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir @@ -2,7 +2,7 @@ --- name: test1BB -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: body: | @@ -26,7 +26,7 @@ body: | --- name: test2BBs -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: body: | diff --git a/llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir b/llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir index 0552c5895ba..9f4ac617cb8 100644 --- a/llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir +++ b/llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir @@ -144,7 +144,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -187,7 +187,7 @@ body: | ... --- name: baz -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -261,7 +261,7 @@ body: | ... --- name: test -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir index a12fdea0a17..f12e4922f34 100644 --- a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir +++ b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir @@ -151,7 +151,7 @@ ... --- name: fun -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -209,7 +209,7 @@ body: | ... --- name: len -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir index 87e99f9404c..213f18611a4 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir @@ -31,7 +31,7 @@ ... --- name: test -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: stackSize: 40 diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir index c834ba056c1..0add9f1c793 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir @@ -29,7 +29,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: maxAlignment: 8 diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir index aac6dbfe5da..e2373089f1b 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir @@ -17,7 +17,7 @@ ... --- name: test -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: stackSize: 4 diff --git a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir index 59275f5cde1..4083e889cc0 100644 --- a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir +++ b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir @@ -32,7 +32,7 @@ ... --- name: test -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: stackSize: 40 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir index a131e19fc90..a4caa06324b 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir @@ -7,7 +7,7 @@ ... --- name: add_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir index 710b00ef7a6..5dd195f4789 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir @@ -15,7 +15,7 @@ ... --- name: and_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -39,7 +39,7 @@ body: | ... --- name: or_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -63,7 +63,7 @@ body: | ... --- name: xor_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -87,7 +87,7 @@ body: | ... --- name: shl -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -110,7 +110,7 @@ body: | ... --- name: ashr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -133,7 +133,7 @@ body: | ... --- name: lshr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -156,7 +156,7 @@ body: | ... --- name: shlv -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -180,7 +180,7 @@ body: | ... --- name: ashrv -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -204,7 +204,7 @@ body: | ... --- name: lshrv -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir index 89fbc624684..a3686f90cc9 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir @@ -26,7 +26,7 @@ ... --- name: Unconditional_branch -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -59,7 +59,7 @@ body: | ... --- name: Conditional_branch -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir index 94dc527a777..8a65fc8e558 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/constants.mir @@ -10,7 +10,7 @@ ... --- name: _0xABCD0000 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -27,7 +27,7 @@ body: | ... --- name: _0x00008000 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -44,7 +44,7 @@ body: | ... --- name: _0xFFFFFFF6 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -61,7 +61,7 @@ body: | ... --- name: _0x0A0B0C0D -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir index 9f820fd4d7b..98423ed86b1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir @@ -9,7 +9,7 @@ ... --- name: fabs_f32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -37,7 +37,7 @@ body: | ... --- name: fabs_f64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir index b861dc6d493..03fa8c8789d 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fcmp.mir @@ -40,7 +40,7 @@ ... --- name: false_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -66,7 +66,7 @@ body: | ... --- name: true_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -92,7 +92,7 @@ body: | ... --- name: uno_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -128,7 +128,7 @@ body: | ... --- name: ord_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -164,7 +164,7 @@ body: | ... --- name: oeq_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -200,7 +200,7 @@ body: | ... --- name: une_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -236,7 +236,7 @@ body: | ... --- name: ueq_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -272,7 +272,7 @@ body: | ... --- name: one_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -308,7 +308,7 @@ body: | ... --- name: olt_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -344,7 +344,7 @@ body: | ... --- name: uge_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -380,7 +380,7 @@ body: | ... --- name: ult_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -416,7 +416,7 @@ body: | ... --- name: oge_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -452,7 +452,7 @@ body: | ... --- name: ole_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -488,7 +488,7 @@ body: | ... --- name: ugt_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -524,7 +524,7 @@ body: | ... --- name: ule_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -560,7 +560,7 @@ body: | ... --- name: ogt_s -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -596,7 +596,7 @@ body: | ... --- name: false_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -622,7 +622,7 @@ body: | ... --- name: true_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -648,7 +648,7 @@ body: | ... --- name: uno_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -684,7 +684,7 @@ body: | ... --- name: ord_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -720,7 +720,7 @@ body: | ... --- name: oeq_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -756,7 +756,7 @@ body: | ... --- name: une_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -792,7 +792,7 @@ body: | ... --- name: ueq_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -828,7 +828,7 @@ body: | ... --- name: one_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -864,7 +864,7 @@ body: | ... --- name: olt_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -900,7 +900,7 @@ body: | ... --- name: uge_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -936,7 +936,7 @@ body: | ... --- name: ult_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -972,7 +972,7 @@ body: | ... --- name: oge_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1008,7 +1008,7 @@ body: | ... --- name: ole_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1044,7 +1044,7 @@ body: | ... --- name: ugt_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1080,7 +1080,7 @@ body: | ... --- name: ule_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1116,7 +1116,7 @@ body: | ... --- name: ogt_d -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir index 5a277be4d91..8595c136eef 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir @@ -7,7 +7,7 @@ ... --- name: atomic_load_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir index a81888ab49b..62d86990a3a 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_args.mir @@ -15,7 +15,7 @@ ... --- name: float_in_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -40,7 +40,7 @@ body: | ... --- name: double_in_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -65,7 +65,7 @@ body: | ... --- name: float_in_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -90,7 +90,7 @@ body: | ... --- name: double_in_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -115,7 +115,7 @@ body: | ... --- name: call_float_in_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -161,7 +161,7 @@ body: | ... --- name: call_double_in_fpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -207,7 +207,7 @@ body: | ... --- name: call_float_in_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -253,7 +253,7 @@ body: | ... --- name: call_double_in_gpr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir index 8f20f089633..2654952dc28 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_arithmetic_operations.mir @@ -15,7 +15,7 @@ ... --- name: float_add -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -46,7 +46,7 @@ body: | ... --- name: float_sub -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -77,7 +77,7 @@ body: | ... --- name: float_mul -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -108,7 +108,7 @@ body: | ... --- name: float_div -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -139,7 +139,7 @@ body: | ... --- name: double_add -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -170,7 +170,7 @@ body: | ... --- name: double_sub -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -201,7 +201,7 @@ body: | ... --- name: double_mul -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -232,7 +232,7 @@ body: | ... --- name: double_div -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_constants.mir index 4fa62807602..7b007e8906b 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_constants.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/float_constants.mir @@ -9,7 +9,7 @@ ... --- name: e_single_precision -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -34,7 +34,7 @@ body: | ... --- name: e_double_precision -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir index a2763ca3f98..053da198abe 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir @@ -9,7 +9,7 @@ ... --- name: fpext -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -37,7 +37,7 @@ body: | ... --- name: fptrunc -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir index 0d93355c2cd..32eab52adbd 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fptosi_and_fptoui.mir @@ -9,7 +9,7 @@ ... --- name: f32toi32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -39,7 +39,7 @@ body: | ... --- name: f64toi32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir index a77f2875350..0759fc1ab5c 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir @@ -9,7 +9,7 @@ ... --- name: sqrt_f32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -37,7 +37,7 @@ body: | ... --- name: sqrt_f64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir index 3ed8a298451..f4d065a2054 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir @@ -10,7 +10,7 @@ ... --- name: main -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir index d91a36e6004..0babd2bd5c2 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address_pic.mir @@ -15,7 +15,7 @@ ... --- name: f_with_local_linkage -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -39,7 +39,7 @@ body: | ... --- name: call_global -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -80,7 +80,7 @@ body: | ... --- name: call_global_with_local_linkage -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -122,7 +122,7 @@ body: | ... --- name: ret_global_int -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -143,7 +143,7 @@ body: | ... --- name: ret_global_int_with_local_linkage -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir index 0e6f1211b2b..833adb8721c 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir @@ -18,7 +18,7 @@ ... --- name: eq_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -44,7 +44,7 @@ body: | ... --- name: ne_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -70,7 +70,7 @@ body: | ... --- name: sgt_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -95,7 +95,7 @@ body: | ... --- name: sge_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -121,7 +121,7 @@ body: | ... --- name: slt_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -146,7 +146,7 @@ body: | ... --- name: sle_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -172,7 +172,7 @@ body: | ... --- name: ugt_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -197,7 +197,7 @@ body: | ... --- name: uge_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -223,7 +223,7 @@ body: | ... --- name: ult_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -248,7 +248,7 @@ body: | ... --- name: ule_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -274,7 +274,7 @@ body: | ... --- name: eq_ptr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir index 2add4dc1c61..e56b48ba560 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/inttoptr_and_ptrtoint.mir @@ -8,7 +8,7 @@ ... --- name: inttoptr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -29,7 +29,7 @@ body: | ... --- name: ptrtoint -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir index e3e198735a8..d9c6f0d8324 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir @@ -58,7 +58,7 @@ ... --- name: mod4_0_to_11 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir index ff9c1d5ccca..7039b271f73 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir @@ -10,7 +10,7 @@ ... --- name: load_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -38,7 +38,7 @@ body: | ... --- name: load_float -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -66,7 +66,7 @@ body: | ... --- name: load_double -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir index 11c4d1f5541..d455825ba7f 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_fold.mir @@ -14,7 +14,7 @@ ... --- name: _16_bit_positive_offset -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -38,7 +38,7 @@ body: | ... --- name: _16_bit_negative_offset -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -63,7 +63,7 @@ body: | ... --- name: _large_positive_offset -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -90,7 +90,7 @@ body: | ... --- name: _large_negative_offset -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -117,7 +117,7 @@ body: | ... --- name: fold_f32_load -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -141,7 +141,7 @@ body: | ... --- name: fold_f64_store -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -165,7 +165,7 @@ body: | ... --- name: fold_i16_load -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -189,7 +189,7 @@ body: | ... --- name: fold_i32_store -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir index 6b4246b35bc..41bd42d691a 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir @@ -8,7 +8,7 @@ ... --- name: mul_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -32,7 +32,7 @@ body: | ... --- name: umul_with_overflow -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir index 49675654361..e907f79824e 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir @@ -66,7 +66,7 @@ ... --- name: phi_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -136,7 +136,7 @@ body: | ... --- name: phi_i64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -227,7 +227,7 @@ body: | ... --- name: phi_float -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -297,7 +297,7 @@ body: | ... --- name: phi_double -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir index 5995c7f5144..ef214f11efa 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir @@ -9,7 +9,7 @@ ... --- name: ptr_arg_in_regs -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -31,7 +31,7 @@ body: | ... --- name: ptr_arg_on_stack -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -61,7 +61,7 @@ body: | ... --- name: ret_ptr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir index 55594330836..67e80d0c364 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div.mir @@ -10,7 +10,7 @@ ... --- name: sdiv_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -35,7 +35,7 @@ body: | ... --- name: srem_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -60,7 +60,7 @@ body: | ... --- name: udiv_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -85,7 +85,7 @@ body: | ... --- name: urem_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir index c0271fcbc06..904def3a69f 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir @@ -11,7 +11,7 @@ ... --- name: select_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -52,7 +52,7 @@ body: | ... --- name: select_ptr -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -93,7 +93,7 @@ body: | ... --- name: select_float -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -134,7 +134,7 @@ body: | ... --- name: select_double -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir index 9f0e455590b..edeb3966d86 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sitofp_and_uitofp.mir @@ -9,7 +9,7 @@ ... --- name: i32tof32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -37,7 +37,7 @@ body: | ... --- name: i32tof64 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir index 78d05004da4..8de38342397 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/stack_args.mir @@ -8,7 +8,7 @@ ... --- name: g -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir index aa4e6527af3..bf9f946211b 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir @@ -10,7 +10,7 @@ ... --- name: store_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -38,7 +38,7 @@ body: | ... --- name: store_float -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -66,7 +66,7 @@ body: | ... --- name: store_double -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir index 911073a7f8d..9e0fd5129e5 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub.mir @@ -7,7 +7,7 @@ ... --- name: sub_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir index 4e700bb3f1a..0d94ef27276 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir @@ -9,7 +9,7 @@ ... --- name: load_store_i8 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -34,7 +34,7 @@ body: | ... --- name: load_store_i16 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -59,7 +59,7 @@ body: | ... --- name: load_store_i32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir index 168bc53309d..f6a6598a76a 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir @@ -10,7 +10,7 @@ ... --- name: load1_s8_to_zextLoad1_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -32,7 +32,7 @@ body: | ... --- name: load2_s16_to_zextLoad2_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -76,7 +76,7 @@ body: | ... --- name: load2_s16_to_sextLoad2_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir index b9b6289d729..6ee5f2a4b18 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir @@ -16,7 +16,7 @@ ... --- name: add_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0.entry: @@ -38,7 +38,7 @@ body: | ... --- name: add_i8_sext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -69,7 +69,7 @@ body: | ... --- name: add_i8_zext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -99,7 +99,7 @@ body: | ... --- name: add_i8_aext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -127,7 +127,7 @@ body: | ... --- name: add_i16_sext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -158,7 +158,7 @@ body: | ... --- name: add_i16_zext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -188,7 +188,7 @@ body: | ... --- name: add_i16_aext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -216,7 +216,7 @@ body: | ... --- name: add_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -253,7 +253,7 @@ body: | ... --- name: add_i128 -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: default, isImmutable: true } @@ -325,7 +325,7 @@ body: | ... --- name: uadd_with_overflow -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir index 9a6135a2211..7901de7ea6d 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir @@ -34,7 +34,7 @@ ... --- name: and_i1 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -62,7 +62,7 @@ body: | ... --- name: and_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -90,7 +90,7 @@ body: | ... --- name: and_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -118,7 +118,7 @@ body: | ... --- name: and_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -140,7 +140,7 @@ body: | ... --- name: and_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -172,7 +172,7 @@ body: | ... --- name: or_i1 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -200,7 +200,7 @@ body: | ... --- name: or_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -228,7 +228,7 @@ body: | ... --- name: or_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -256,7 +256,7 @@ body: | ... --- name: or_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -278,7 +278,7 @@ body: | ... --- name: or_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -310,7 +310,7 @@ body: | ... --- name: xor_i1 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -338,7 +338,7 @@ body: | ... --- name: xor_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -366,7 +366,7 @@ body: | ... --- name: xor_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -394,7 +394,7 @@ body: | ... --- name: xor_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -416,7 +416,7 @@ body: | ... --- name: xor_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -448,7 +448,7 @@ body: | ... --- name: shl -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -470,7 +470,7 @@ body: | ... --- name: ashr -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -492,7 +492,7 @@ body: | ... --- name: lshr -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -514,7 +514,7 @@ body: | ... --- name: lshr_i64_shift_amount -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -538,7 +538,7 @@ body: | ... --- name: shlv -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -560,7 +560,7 @@ body: | ... --- name: ashrv -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -582,7 +582,7 @@ body: | ... --- name: lshrv -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -604,7 +604,7 @@ body: | ... --- name: shl_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -633,7 +633,7 @@ body: | ... --- name: ashr_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -665,7 +665,7 @@ body: | ... --- name: lshr_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -695,7 +695,7 @@ body: | ... --- name: shl_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -747,7 +747,7 @@ body: | ... --- name: ashl_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -801,7 +801,7 @@ body: | ... --- name: lshr_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir index b1a4b4b9fcd..566e2fcbfe5 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir @@ -26,7 +26,7 @@ ... --- name: Unconditional_branch -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; MIPS32-LABEL: name: Unconditional_branch @@ -57,7 +57,7 @@ body: | ... --- name: Conditional_branch -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; MIPS32-LABEL: name: Conditional_branch diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir index f7e39f3885b..d1570fb8bb1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir @@ -11,7 +11,7 @@ ... --- name: ceil_f32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -45,7 +45,7 @@ body: | ... --- name: ceil_f64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -79,7 +79,7 @@ body: | ... --- name: floor_f32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -113,7 +113,7 @@ body: | ... --- name: floor_f64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir index a2b754ad3fc..5a805af18de 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir @@ -14,7 +14,7 @@ ... --- name: any_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -33,7 +33,7 @@ body: | ... --- name: any_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -48,7 +48,7 @@ body: | ... --- name: signed_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -68,7 +68,7 @@ body: | ... --- name: signed_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -88,7 +88,7 @@ body: | ... --- name: unsigned_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -107,7 +107,7 @@ body: | ... --- name: unsigned_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -126,7 +126,7 @@ body: | ... --- name: i1_true -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -145,7 +145,7 @@ body: | ... --- name: i1_false -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir index ffed3b23656..1e9e9f0bb96 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir @@ -9,7 +9,7 @@ ... --- name: fabs_f32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -35,7 +35,7 @@ body: | ... --- name: fabs_f64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir index 9df4edd2ad1..26e8a883081 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir @@ -9,7 +9,7 @@ ... --- name: oeq_s -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -41,7 +41,7 @@ body: | ... --- name: oeq_d -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir index 9e04de27b03..3a5e42bbb01 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir @@ -7,7 +7,7 @@ ... --- name: atomic_load_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir index 7ce699cdf40..b7dc1a6a276 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_arithmetic_operations.mir @@ -16,7 +16,7 @@ ... --- name: float_add -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -45,7 +45,7 @@ body: | ... --- name: float_sub -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -74,7 +74,7 @@ body: | ... --- name: float_mul -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -103,7 +103,7 @@ body: | ... --- name: float_div -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -132,7 +132,7 @@ body: | ... --- name: double_add -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -161,7 +161,7 @@ body: | ... --- name: double_sub -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -190,7 +190,7 @@ body: | ... --- name: double_mul -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -219,7 +219,7 @@ body: | ... --- name: double_div -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir index 695a8ff8d6d..923c41ecaaf 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/float_constants.mir @@ -10,7 +10,7 @@ ... --- name: e_single_precision -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -29,7 +29,7 @@ body: | ... --- name: e_double_precision -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir index ba4a81d0684..38d8313b4f6 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fpext_and_fptrunc.mir @@ -9,7 +9,7 @@ ... --- name: fpext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -35,7 +35,7 @@ body: | ... --- name: fptrunc -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir index 35eaf3d6470..829273b026e 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir @@ -23,7 +23,7 @@ ... --- name: f32toi64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -63,7 +63,7 @@ body: | ... --- name: f32toi32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -89,7 +89,7 @@ body: | ... --- name: f32toi16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -124,7 +124,7 @@ body: | ... --- name: f32toi8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -159,7 +159,7 @@ body: | ... --- name: f64toi64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -199,7 +199,7 @@ body: | ... --- name: f64toi32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -225,7 +225,7 @@ body: | ... --- name: f64toi16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -260,7 +260,7 @@ body: | ... --- name: f64toi8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -295,7 +295,7 @@ body: | ... --- name: f32tou64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -335,7 +335,7 @@ body: | ... --- name: f32tou32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -375,7 +375,7 @@ body: | ... --- name: f32tou16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -422,7 +422,7 @@ body: | ... --- name: f32tou8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -469,7 +469,7 @@ body: | ... --- name: f64tou64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -509,7 +509,7 @@ body: | ... --- name: f64tou32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -549,7 +549,7 @@ body: | ... --- name: f64tou16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -596,7 +596,7 @@ body: | ... --- name: f64tou8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir index 186498a3af1..f65cedf4650 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir @@ -9,7 +9,7 @@ ... --- name: sqrt_f32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -35,7 +35,7 @@ body: | ... --- name: sqrt_f64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir index 9fcc82164b1..2056eda04fa 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir @@ -10,7 +10,7 @@ ... --- name: main -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir index b25b0720640..e813778035c 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir @@ -20,7 +20,7 @@ ... --- name: ne_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -44,7 +44,7 @@ body: | ... --- name: eq_ptr -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -68,7 +68,7 @@ body: | ... --- name: ult_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -99,7 +99,7 @@ body: | ... --- name: slt_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -132,7 +132,7 @@ body: | ... --- name: eq_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -166,7 +166,7 @@ body: | ... --- name: ne_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -200,7 +200,7 @@ body: | ... --- name: sgt_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -238,7 +238,7 @@ body: | ... --- name: sge_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -276,7 +276,7 @@ body: | ... --- name: slt_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -314,7 +314,7 @@ body: | ... --- name: sle_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -352,7 +352,7 @@ body: | ... --- name: ugt_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -390,7 +390,7 @@ body: | ... --- name: uge_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -428,7 +428,7 @@ body: | ... --- name: ult_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -466,7 +466,7 @@ body: | ... --- name: ule_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir index 5e1fcc8aa78..4d34f21d258 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/inttoptr_and_ptrtoint.mir @@ -8,7 +8,7 @@ ... --- name: inttoptr -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -28,7 +28,7 @@ body: | ... --- name: ptrtoint -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir index eff11a4ac7f..71332f64b99 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir @@ -57,7 +57,7 @@ ... --- name: mod4_0_to_11 -alignment: 2 +alignment: 4 tracksRegLiveness: true jumpTable: kind: block-address diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir index 990f74ad0b8..b0365f7c87d 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/load.mir @@ -10,7 +10,7 @@ ... --- name: load_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -30,7 +30,7 @@ body: | ... --- name: load_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -54,7 +54,7 @@ body: | ... --- name: load_float -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -74,7 +74,7 @@ body: | ... --- name: load_double -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir index 351bf5efcdf..c92a55d0af3 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir @@ -17,7 +17,7 @@ ... --- name: mul_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.0.entry: @@ -39,7 +39,7 @@ body: | ... --- name: mul_i8_sext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -70,7 +70,7 @@ body: | ... --- name: mul_i8_zext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -100,7 +100,7 @@ body: | ... --- name: mul_i8_aext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -128,7 +128,7 @@ body: | ... --- name: mul_i16_sext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -159,7 +159,7 @@ body: | ... --- name: mul_i16_zext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -189,7 +189,7 @@ body: | ... --- name: mul_i16_aext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -217,7 +217,7 @@ body: | ... --- name: mul_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -253,7 +253,7 @@ body: | ... --- name: mul_i128 -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: default, isImmutable: true } @@ -365,7 +365,7 @@ body: | ... --- name: umulh_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -427,7 +427,7 @@ body: | ... --- name: umul_with_overflow -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1 (%ir-block.0): diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir index f8cca3ace6d..34d3f3e9160 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir @@ -110,7 +110,7 @@ ... --- name: phi_i1 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; MIPS32-LABEL: name: phi_i1 @@ -163,7 +163,7 @@ body: | ... --- name: phi_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; MIPS32-LABEL: name: phi_i8 @@ -216,7 +216,7 @@ body: | ... --- name: phi_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; MIPS32-LABEL: name: phi_i16 @@ -269,7 +269,7 @@ body: | ... --- name: phi_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; MIPS32-LABEL: name: phi_i32 @@ -316,7 +316,7 @@ body: | ... --- name: phi_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true } @@ -382,7 +382,7 @@ body: | ... --- name: phi_float -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | ; MIPS32-LABEL: name: phi_float @@ -429,7 +429,7 @@ body: | ... --- name: phi_double -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir index e42ab031451..1176a25bc20 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir @@ -9,7 +9,7 @@ ... --- name: ptr_arg_in_regs -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -29,7 +29,7 @@ body: | ... --- name: ptr_arg_on_stack -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true } @@ -61,7 +61,7 @@ body: | ... --- name: ret_ptr -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir index 57b234d0f9b..7acfc9eb71f 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir @@ -22,7 +22,7 @@ ... --- name: sdiv_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -57,7 +57,7 @@ body: | ... --- name: sdiv_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -92,7 +92,7 @@ body: | ... --- name: sdiv_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -114,7 +114,7 @@ body: | ... --- name: sdiv_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -153,7 +153,7 @@ body: | ... --- name: srem_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -188,7 +188,7 @@ body: | ... --- name: srem_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -223,7 +223,7 @@ body: | ... --- name: srem_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -245,7 +245,7 @@ body: | ... --- name: srem_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -284,7 +284,7 @@ body: | ... --- name: udiv_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -318,7 +318,7 @@ body: | ... --- name: udiv_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -352,7 +352,7 @@ body: | ... --- name: udiv_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -374,7 +374,7 @@ body: | ... --- name: udiv_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -413,7 +413,7 @@ body: | ... --- name: urem_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -447,7 +447,7 @@ body: | ... --- name: urem_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -481,7 +481,7 @@ body: | ... --- name: urem_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -503,7 +503,7 @@ body: | ... --- name: urem_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir index 8d5322dcfa4..59d4280e1ba 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir @@ -14,7 +14,7 @@ ... --- name: select_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -48,7 +48,7 @@ body: | ... --- name: select_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -82,7 +82,7 @@ body: | ... --- name: select_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -110,7 +110,7 @@ body: | ... --- name: select_ptr -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -138,7 +138,7 @@ body: | ... --- name: select_with_negation -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -175,7 +175,7 @@ body: | ... --- name: select_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true } @@ -222,7 +222,7 @@ body: | ... --- name: select_float -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -250,7 +250,7 @@ body: | ... --- name: select_double -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir index 100a88b89df..99c6bbe1ca8 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir @@ -23,7 +23,7 @@ ... --- name: i64tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -63,7 +63,7 @@ body: | ... --- name: i32tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -89,7 +89,7 @@ body: | ... --- name: i16tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -124,7 +124,7 @@ body: | ... --- name: i8tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -159,7 +159,7 @@ body: | ... --- name: i64tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -199,7 +199,7 @@ body: | ... --- name: i32tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -225,7 +225,7 @@ body: | ... --- name: i16tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -260,7 +260,7 @@ body: | ... --- name: i8tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -295,7 +295,7 @@ body: | ... --- name: u64tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -335,7 +335,7 @@ body: | ... --- name: u32tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -371,7 +371,7 @@ body: | ... --- name: u16tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -412,7 +412,7 @@ body: | ... --- name: u8tof32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -453,7 +453,7 @@ body: | ... --- name: u64tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -493,7 +493,7 @@ body: | ... --- name: u32tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -527,7 +527,7 @@ body: | ... --- name: u16tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -566,7 +566,7 @@ body: | ... --- name: u8tof64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir index 36d2ed81aa9..e601e8ab366 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/stack_args.mir @@ -8,7 +8,7 @@ ... --- name: g -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 16, size: 4, alignment: 8, stack-id: default, isImmutable: true } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir index ab4c83b286e..e6f45e9b5c1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store.mir @@ -10,7 +10,7 @@ ... --- name: store_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -31,7 +31,7 @@ body: | ... --- name: store_i64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -56,7 +56,7 @@ body: | ... --- name: store_float -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -77,7 +77,7 @@ body: | ... --- name: store_double -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir index 2e02eb07174..3f018e8fce1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir @@ -15,7 +15,7 @@ ... --- name: sub_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -37,7 +37,7 @@ body: | ... --- name: sub_i8_sext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -68,7 +68,7 @@ body: | ... --- name: sub_i8_zext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -98,7 +98,7 @@ body: | ... --- name: sub_i8_aext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -126,7 +126,7 @@ body: | ... --- name: sub_i16_sext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -157,7 +157,7 @@ body: | ... --- name: sub_i16_zext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -187,7 +187,7 @@ body: | ... --- name: sub_i16_aext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -215,7 +215,7 @@ body: | ... --- name: sub_i64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -252,7 +252,7 @@ body: | ... --- name: sub_i128 -alignment: 2 +alignment: 4 tracksRegLiveness: true fixedStack: - { id: 0, offset: 28, size: 4, alignment: 4, stack-id: default, isImmutable: true } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir index 101a12490b7..64388933fda 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir @@ -8,7 +8,7 @@ ... --- name: f -alignment: 2 +alignment: 4 body: | bb.1 (%ir-block.0): ; MIPS32-LABEL: name: f diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir index fb45cc3ea46..34ccfd97e27 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir @@ -7,7 +7,7 @@ ... --- name: trunc -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir index a65d25b6799..740652574c6 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir @@ -12,7 +12,7 @@ ... --- name: load1_s8_to_load1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -32,7 +32,7 @@ body: | ... --- name: load2_s16_to_load2_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -52,7 +52,7 @@ body: | ... --- name: load_store_i1 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -77,7 +77,7 @@ body: | ... --- name: load_store_i8 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -100,7 +100,7 @@ body: | ... --- name: load_store_i16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -123,7 +123,7 @@ body: | ... --- name: load_store_i32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir index 25481182ad2..3e779d7dd27 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir @@ -16,7 +16,7 @@ ... --- name: load1_s8_to_zextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -36,7 +36,7 @@ body: | ... --- name: load2_s16_to_zextLoad2_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -56,7 +56,7 @@ body: | ... --- name: load1_s8_to_zextLoad1_s16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -78,7 +78,7 @@ body: | ... --- name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -98,7 +98,7 @@ body: | ... --- name: load4_s32_to_zextLoad4_s64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -124,7 +124,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -144,7 +144,7 @@ body: | ... --- name: load2_s16_to_sextLoad2_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -164,7 +164,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -186,7 +186,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -206,7 +206,7 @@ body: | ... --- name: load4_s32_to_sextLoad4_s64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir index 2e19ed2987b..93d3c17aac7 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir @@ -8,7 +8,7 @@ ... --- name: zext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -33,7 +33,7 @@ body: | ... --- name: sext -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir index 63b9267325e..a8338fa2435 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir @@ -8,7 +8,7 @@ ... --- name: load1_s8_to_load1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -29,7 +29,7 @@ body: | ... --- name: load2_s16_to_load2_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir index a8b2db19e41..ace678c2400 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/tryCombine.mir @@ -16,7 +16,7 @@ # MIPS32: Try combining $v0 = COPY %2:_(s32) # MIPS32: Try combining RetRA implicit $v0 name: f -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir index 7867a2fa2a7..addd57c330c 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir @@ -16,7 +16,7 @@ ... --- name: load1_s8_to_zextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -37,7 +37,7 @@ body: | ... --- name: load2_s16_to_zextLoad2_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -58,7 +58,7 @@ body: | ... --- name: load1_s8_to_zextLoad1_s16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -81,7 +81,7 @@ body: | ... --- name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -103,7 +103,7 @@ body: | ... --- name: load4_s32_to_zextLoad4_s64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -128,7 +128,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -149,7 +149,7 @@ body: | ... --- name: load2_s16_to_sextLoad2_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -170,7 +170,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s16 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -193,7 +193,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: @@ -215,7 +215,7 @@ body: | ... --- name: load4_s32_to_sextLoad4_s64 -alignment: 2 +alignment: 4 tracksRegLiveness: true body: | bb.1.entry: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir index 284cf74b2fb..bb2a93048c8 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir @@ -8,7 +8,7 @@ ... --- name: skipCopiesOutgoing -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -41,7 +41,7 @@ body: | ... --- name: skipCopiesIncoming -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir index 233d3d45454..a1c41fad425 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add.mir @@ -7,7 +7,7 @@ ... --- name: add_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir index 595b4a18124..e5cc1d9eb7d 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir @@ -16,7 +16,7 @@ ... --- name: and_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -39,7 +39,7 @@ body: | ... --- name: or_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -62,7 +62,7 @@ body: | ... --- name: xor_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -85,7 +85,7 @@ body: | ... --- name: shl -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -108,7 +108,7 @@ body: | ... --- name: ashr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -131,7 +131,7 @@ body: | ... --- name: lshr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -154,7 +154,7 @@ body: | ... --- name: shlv -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -177,7 +177,7 @@ body: | ... --- name: ashrv -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -200,7 +200,7 @@ body: | ... --- name: lshrv -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir index 9c431438356..28416f116d0 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir @@ -26,7 +26,7 @@ ... --- name: Unconditional_branch -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -58,7 +58,7 @@ body: | ... --- name: Conditional_branch -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir index 2db4ca7207d..f7fe5a0a7c0 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir @@ -9,7 +9,7 @@ ... --- name: fabs_f32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -36,7 +36,7 @@ body: | ... --- name: fabs_f64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir index ed5f3dface8..6673980b4b1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir @@ -9,7 +9,7 @@ ... --- name: oeq_s -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -42,7 +42,7 @@ body: | ... --- name: oeq_d -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir index de9502123f0..9fdf17d8a8d 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir @@ -7,7 +7,7 @@ ... --- name: atomic_load_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir index ba4d28ca53a..bca5e826f8e 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir @@ -16,7 +16,7 @@ ... --- name: float_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -40,7 +40,7 @@ body: | ... --- name: double_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -64,7 +64,7 @@ body: | ... --- name: float_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -88,7 +88,7 @@ body: | ... --- name: double_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -112,7 +112,7 @@ body: | ... --- name: call_float_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -157,7 +157,7 @@ body: | ... --- name: call_double_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -202,7 +202,7 @@ body: | ... --- name: call_float_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -247,7 +247,7 @@ body: | ... --- name: call_double_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir index 9c8a64ff306..49bd7702af8 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_arithmetic_operations.mir @@ -16,7 +16,7 @@ ... --- name: float_add -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -46,7 +46,7 @@ body: | ... --- name: float_sub -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -76,7 +76,7 @@ body: | ... --- name: float_mul -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -106,7 +106,7 @@ body: | ... --- name: float_div -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -136,7 +136,7 @@ body: | ... --- name: double_add -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -166,7 +166,7 @@ body: | ... --- name: double_sub -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -196,7 +196,7 @@ body: | ... --- name: double_mul -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -226,7 +226,7 @@ body: | ... --- name: double_div -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir index 87b91405b77..4f0a688990d 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/float_constants.mir @@ -10,7 +10,7 @@ ... --- name: e_single_precision -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -30,7 +30,7 @@ body: | ... --- name: e_double_precision -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir index 04542267f39..52c751e8c47 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fpext_and_fptrunc.mir @@ -9,7 +9,7 @@ ... --- name: fpext -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -36,7 +36,7 @@ body: | ... --- name: fptrunc -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir index 487384fa11f..74c1a7dcc7f 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fptosi_and_fptoui.mir @@ -9,7 +9,7 @@ ... --- name: f32toi32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -36,7 +36,7 @@ body: | ... --- name: f64toi32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir index ba86c15af5c..a9ca2f2515d 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir @@ -9,7 +9,7 @@ ... --- name: sqrt_f32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -36,7 +36,7 @@ body: | ... --- name: sqrt_f64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir index 11815516f64..cf19ddceaac 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir @@ -10,7 +10,7 @@ ... --- name: main -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir index 163c693f2a1..d53b1575ca7 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address_pic.mir @@ -8,7 +8,7 @@ ... --- name: call_global -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir index 797c76a3cd6..611ba0718c1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir @@ -8,7 +8,7 @@ ... --- name: ne_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -33,7 +33,7 @@ body: | ... --- name: eq_ptr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir index 42cd6122c11..b7eda46de75 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/inttoptr_and_ptrtoint.mir @@ -8,7 +8,7 @@ ... --- name: inttoptr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -29,7 +29,7 @@ body: | ... --- name: ptrtoint -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir index 09600148c28..56c629a292c 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir @@ -57,7 +57,7 @@ ... --- name: mod4_0_to_11 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true jumpTable: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir index b5a96584102..0b23b4442c4 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir @@ -12,7 +12,7 @@ ... --- name: load_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -33,7 +33,7 @@ body: | ... --- name: load_i64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -60,7 +60,7 @@ body: | ... --- name: load_ambiguous_i64_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -83,7 +83,7 @@ body: | ... --- name: load_float -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -104,7 +104,7 @@ body: | ... --- name: load_ambiguous_float_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -127,7 +127,7 @@ body: | ... --- name: load_double -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir index e8929ecd7f1..e386efbf45b 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir @@ -241,7 +241,7 @@ ... --- name: long_chain_ambiguous_i64_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -433,7 +433,7 @@ body: | ... --- name: long_chain_i64_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -661,7 +661,7 @@ body: | ... --- name: long_chain_ambiguous_double_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -853,7 +853,7 @@ body: | ... --- name: long_chain_double_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir index e8929ecd7f1..e386efbf45b 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir @@ -241,7 +241,7 @@ ... --- name: long_chain_ambiguous_i64_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -433,7 +433,7 @@ body: | ... --- name: long_chain_i64_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -661,7 +661,7 @@ body: | ... --- name: long_chain_ambiguous_double_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -853,7 +853,7 @@ body: | ... --- name: long_chain_double_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir index dd347142b01..3dea77ea2d5 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir @@ -8,7 +8,7 @@ ... --- name: mul_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -31,7 +31,7 @@ body: | ... --- name: umul_with_overflow -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir index df05dd5dda2..34167e8937f 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir @@ -101,7 +101,7 @@ ... --- name: phi_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -151,7 +151,7 @@ body: | ... --- name: phi_i64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -218,7 +218,7 @@ body: | ... --- name: phi_ambiguous_i64_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -274,7 +274,7 @@ body: | ... --- name: phi_float -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -324,7 +324,7 @@ body: | ... --- name: phi_ambiguous_float_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -380,7 +380,7 @@ body: | ... --- name: phi_double -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir index 1a2f99aedd5..38d94f90311 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir @@ -9,7 +9,7 @@ ... --- name: ptr_arg_in_regs -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -30,7 +30,7 @@ body: | ... --- name: ptr_arg_on_stack -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -63,7 +63,7 @@ body: | ... --- name: ret_ptr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir index bee36309a9f..b9b725e8e13 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div.mir @@ -10,7 +10,7 @@ ... --- name: sdiv_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -33,7 +33,7 @@ body: | ... --- name: srem_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -56,7 +56,7 @@ body: | ... --- name: udiv_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -79,7 +79,7 @@ body: | ... --- name: urem_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir index 4c8ccbb9b07..6c1761c6ad2 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir @@ -13,7 +13,7 @@ ... --- name: select_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -44,7 +44,7 @@ body: | ... --- name: select_ptr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -75,7 +75,7 @@ body: | ... --- name: select_i64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: @@ -123,7 +123,7 @@ body: | ... --- name: select_ambiguous_i64_in_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -160,7 +160,7 @@ body: | ... --- name: select_float -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -191,7 +191,7 @@ body: | ... --- name: select_ambiguous_float_in_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -228,7 +228,7 @@ body: | ... --- name: select_double -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir index 253e7d9fb70..2d5b7991dbf 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sitofp_and_uitofp.mir @@ -9,7 +9,7 @@ ... --- name: i32tof32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -36,7 +36,7 @@ body: | ... --- name: i32tof64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir index 80c66bc2790..bdbd462b027 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/stack_args.mir @@ -8,7 +8,7 @@ ... --- name: g -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true fixedStack: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir index 03c5a867f4b..b0d8b072d49 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir @@ -10,7 +10,7 @@ ... --- name: store_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -31,7 +31,7 @@ body: | ... --- name: store_i64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -58,7 +58,7 @@ body: | ... --- name: store_float -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -79,7 +79,7 @@ body: | ... --- name: store_double -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir index 487024783e6..dcee70ce4b0 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub.mir @@ -7,7 +7,7 @@ ... --- name: sub_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir index 4702531cd52..234a5607112 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir @@ -14,7 +14,7 @@ ... --- name: outgoing_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -35,7 +35,7 @@ body: | ... --- name: outgoing_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -56,7 +56,7 @@ body: | ... --- name: outgoing_gpr_instr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -83,7 +83,7 @@ body: | ... --- name: outgoing_fpr_instr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -110,7 +110,7 @@ body: | ... --- name: incoming_gpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -143,7 +143,7 @@ body: | ... --- name: incoming_fpr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -176,7 +176,7 @@ body: | ... --- name: incoming_i32_instr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -213,7 +213,7 @@ body: | ... --- name: incoming_float_instr -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir index 9b4d903434e..049cae33c41 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir @@ -9,7 +9,7 @@ ... --- name: load_store_i8 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -34,7 +34,7 @@ body: | ... --- name: load_store_i16 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -59,7 +59,7 @@ body: | ... --- name: load_store_i32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir index ee77cfcea76..057cf93aba1 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir @@ -12,7 +12,7 @@ ... --- name: load1_s8_to_zextLoad1_s32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -33,7 +33,7 @@ body: | ... --- name: load2_s16_to_zextLoad2_s32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -54,7 +54,7 @@ body: | ... --- name: load4_s32_to_zextLoad4_s64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -81,7 +81,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -102,7 +102,7 @@ body: | ... --- name: load2_s16_to_sextLoad2_s32 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -123,7 +123,7 @@ body: | ... --- name: load4_s32_to_sextLoad4_s64 -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir index 149219acd7e..187b3e68b1b 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir @@ -8,7 +8,7 @@ ... --- name: zext -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | @@ -33,7 +33,7 @@ body: | ... --- name: sext -alignment: 2 +alignment: 4 legalized: true tracksRegLiveness: true body: | diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir index 778e08a4cf3..3ae01117f9b 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir +++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir @@ -55,7 +55,7 @@ # CHECK-NEXT: nop # CHECK: blezc name: f -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir index 83c489de1e7..5e9eb680faa 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir +++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir @@ -37,7 +37,7 @@ --- name: l5 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir index 92e26186f45..b1d177a22ea 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir @@ -15,7 +15,7 @@ ... --- name: fooTail -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir index 38a5fb4ee26..e13c93bec24 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir @@ -16,7 +16,7 @@ ... --- name: fooTail -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir index 3db06f70a9d..a93231b72a0 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 0..31 --- name: dext -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir index c66050ae159..6ba7243cdfb 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 1..32 --- name: dext -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir index 14b9da27821..fbf84819a0f 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the pos + size is in the range 33..64 --- name: dextm -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir index e8ca6179257..d4cf55bf6ca 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 0..31 --- name: dextm -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir index 1136281a633..cd9fd2de915 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 33..64 --- name: dextm -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir index f70f3fe8764..782596ec4ec 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the pos + size is in the range 33..64 --- name: dextu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir index 2f01b5ad534..418c98f44fd 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 32..63 --- name: dextu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir index da6444914b0..6663b96494a 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 1..32 --- name: dextu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir index 2958c5d272d..70f12dd1a91 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 1..32 --- name: dextu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir index e4cfd7c21d7..ec6f24aed18 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the pos + size is in the range 1..32 --- name: dins -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir index 05aaf2d2fd5..13a7c6536da 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 0..31 --- name: dins -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir index 2227d6f8043..63e6f9193c9 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 1..32 --- name: dins -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir index 0b8399724bd..bec2fc03431 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the pos + size is in the range 33..64 --- name: dinsu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir index 6f92d790c53..90dced0435d 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 0..31 --- name: dinsm -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir index e7872360cb7..9c8c247f9ea 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 2..64 --- name: dinsm -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir index 503199c50ad..4209a8ddf61 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the pos + size is in the range 33..64 --- name: dinsu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir index 2a81501d24a..7d4828d9294 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 32..63 --- name: dinsu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir index 198bd09d75f..d4c2f56c408 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 1..32 --- name: dinsu -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir index b2f1cf02454..b9c1d6193c9 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the pos + size is in the range 1..32 --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir index 69f817258a3..23cede00d31 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 0..31 --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir index 460956ab46b..8b8ae45ded4 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 1..32 --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir index b6202f5b3a9..9220bbdb747 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the pos + size is in the range 1..32 --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir index 3b7fd0699c0..3932d174be9 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the position operand is in the range 0..31 --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir index 0e17e20eed8..4f5348c2951 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir @@ -6,7 +6,7 @@ # Check that the machine verifier checks the size operand is in the range 1..32 --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir index 1e336a810e9..2411f65b175 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir @@ -35,7 +35,7 @@ ... --- name: a -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -135,7 +135,7 @@ body: | ... --- name: b -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir index 2f05c6b7ab5..9d671348050 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir @@ -35,7 +35,7 @@ ... --- name: a -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -127,7 +127,7 @@ body: | ... --- name: b -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir index 0e34890c5ef..802acab0619 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir @@ -34,7 +34,7 @@ ... --- name: a -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -138,7 +138,7 @@ body: | ... --- name: b -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir index 9b2e9c53fb3..5356ea43485 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir @@ -36,7 +36,7 @@ ... --- name: a -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -136,7 +136,7 @@ body: | ... --- name: b -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir index 53d729144a7..30c9e66a5e7 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir @@ -97,7 +97,7 @@ --- name: expand_BEQ_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -188,7 +188,7 @@ body: | --- name: expand_BGEZ_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -283,7 +283,7 @@ body: | --- name: expand_BGTZ_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -378,7 +378,7 @@ body: | --- name: expand_BLEZ_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -473,7 +473,7 @@ body: | --- name: expand_BLTZ_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -568,7 +568,7 @@ body: | --- name: expand_BNE_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -659,7 +659,7 @@ body: | --- name: expand_BEQZ16_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -754,7 +754,7 @@ body: | --- name: expand_BNEZ16_MM -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir index 0db8ddc1442..67ac46cbe58 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir @@ -141,7 +141,7 @@ --- name: expand_BEQC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -228,7 +228,7 @@ body: | --- name: expand_BNEC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -315,7 +315,7 @@ body: | --- name: expand_BGEC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -402,7 +402,7 @@ body: | --- name: expand_BGEUC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -489,7 +489,7 @@ body: | --- name: expand_BGEZC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -576,7 +576,7 @@ body: | --- name: expand_BGTZC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -663,7 +663,7 @@ body: | --- name: expand_BLEZC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -750,7 +750,7 @@ body: | --- name: expand_BLTC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -837,7 +837,7 @@ body: | --- name: expand_BLTUC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -924,7 +924,7 @@ body: | --- name: expand_BLTZC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1011,7 +1011,7 @@ body: | --- name: expand_BEQZC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1098,7 +1098,7 @@ body: | --- name: expand_BNEZC_MMR6 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir index df846ac487f..38dea077ffc 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir @@ -81,7 +81,7 @@ --- name: expand_BEQ64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -183,7 +183,7 @@ body: | --- name: expand_BNE64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -285,7 +285,7 @@ body: | --- name: expand_BGEZ64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -387,7 +387,7 @@ body: | --- name: expand_BGTZ64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -489,7 +489,7 @@ body: | --- name: expand_BLEZ64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -591,7 +591,7 @@ body: | --- name: expand_BLTZ64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir index 57ed562dd36..9df57064b63 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir @@ -153,7 +153,7 @@ --- name: expand_BNEZC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -230,7 +230,7 @@ body: | --- name: expand_BEQZC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -307,7 +307,7 @@ body: | --- name: expand_BNEC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -405,7 +405,7 @@ body: | --- name: expand_BEQC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -503,7 +503,7 @@ body: | --- name: expand_BLTC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -601,7 +601,7 @@ body: | --- name: expand_BLTUC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -699,7 +699,7 @@ body: | --- name: expand_BGEC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -797,7 +797,7 @@ body: | --- name: expand_BGEUC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -895,7 +895,7 @@ body: | --- name: expand_BLEZC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -993,7 +993,7 @@ body: | --- name: expand_BLTZC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1091,7 +1091,7 @@ body: | --- name: expand_BGEZC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1189,7 +1189,7 @@ body: | --- name: expand_BGTZC64 -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir index f945014a53b..bc110992c57 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir @@ -141,7 +141,7 @@ --- name: expand_BEQC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -228,7 +228,7 @@ body: | --- name: expand_BNEC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -315,7 +315,7 @@ body: | --- name: expand_BGEC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -402,7 +402,7 @@ body: | --- name: expand_BGEUC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -489,7 +489,7 @@ body: | --- name: expand_BGEZC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -576,7 +576,7 @@ body: | --- name: expand_BGTZC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -663,7 +663,7 @@ body: | --- name: expand_BLEZC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -750,7 +750,7 @@ body: | --- name: expand_BLTC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -837,7 +837,7 @@ body: | --- name: expand_BLTUC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -924,7 +924,7 @@ body: | --- name: expand_BLTZC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1011,7 +1011,7 @@ body: | --- name: expand_BEQZC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1098,7 +1098,7 @@ body: | --- name: expand_BNEZC -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir index 3d8a6dd898b..41e3e51db73 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir @@ -75,7 +75,7 @@ --- name: expand_BEQ -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -174,7 +174,7 @@ body: | --- name: expand_BGEZ -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -273,7 +273,7 @@ body: | --- name: expand_BGTZ -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -372,7 +372,7 @@ body: | --- name: expand_BLEZ -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -471,7 +471,7 @@ body: | --- name: expand_BLTZ -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -570,7 +570,7 @@ body: | --- name: expand_BNE -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir index 67e5110298e..a2ceff05b85 100644 --- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir +++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir @@ -221,7 +221,7 @@ ... --- name: _Z4bz_8Dv16_a -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -338,7 +338,7 @@ body: | ... --- name: _Z5bz_16Dv8_s -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -452,7 +452,7 @@ body: | ... --- name: _Z5bz_32Dv4_i -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -566,7 +566,7 @@ body: | ... --- name: _Z5bz_64Dv2_x -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -677,7 +677,7 @@ body: | ... --- name: _Z5bz_64_vDv2_x -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -788,7 +788,7 @@ body: | ... --- name: _Z5bnz_8Dv16_a -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -905,7 +905,7 @@ body: | ... --- name: _Z6bnz_16Dv8_s -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1019,7 +1019,7 @@ body: | ... --- name: _Z6bnz_32Dv4_i -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1133,7 +1133,7 @@ body: | ... --- name: _Z6bnz_64Dv2_x -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1244,7 +1244,7 @@ body: | ... --- name: _Z6bnz_64_vDv2_x -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/micromips-eva.mir b/llvm/test/CodeGen/Mips/micromips-eva.mir index 7f0ae721b36..3210d584fc8 100644 --- a/llvm/test/CodeGen/Mips/micromips-eva.mir +++ b/llvm/test/CodeGen/Mips/micromips-eva.mir @@ -52,7 +52,7 @@ ... --- name: _Z3foov -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -124,7 +124,7 @@ body: | ... --- name: _Z3barPi -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir index df6ca433a7d..f242ea5bd86 100644 --- a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir +++ b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir @@ -20,7 +20,7 @@ ... --- name: caller13 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir index 4bdfa054852..bc5dc6cd7e8 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir @@ -19,7 +19,7 @@ # CHECK: SWP_MM # CHECK: LWP_MM name: f1 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -87,7 +87,7 @@ body: | # CHECK: SWP_MM # CHECK: LWP_MM name: f2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -155,7 +155,7 @@ body: | # CHECK: SWP_MM # CHECK: LWP_MM name: f3 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -223,7 +223,7 @@ body: | # CHECK: SWP_MM # CHECK: LWP_MM name: f4 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir index a6423f4180d..880c89ec315 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir @@ -18,7 +18,7 @@ # CHECK-NOT: SWP_MM # CHECK-NOT: LWP_MM name: f1 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -77,7 +77,7 @@ body: | # CHECK-NOT: SWP_MM # CHECK-NOT: LWP_MM name: f2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -136,7 +136,7 @@ body: | # CHECK-NOT: SWP_MM # CHECK-NOT: LWP_MM name: f3 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -195,7 +195,7 @@ body: | # CHECK-NOT: SWP_MM # CHECK-NOT: LWP_MM name: f4 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir index dfc5bffb7ae..2956a175dd7 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir @@ -51,7 +51,7 @@ ... --- name: _Z2k1i -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir index a34efa9fdfd..5e10a84ddc0 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir @@ -24,7 +24,7 @@ ... --- name: _Z2k1i -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir index 5ec96c411fb..7592ef9f66b 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir @@ -24,7 +24,7 @@ ... --- name: _Z2k1i -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir index 5630926aadf..b35dde33fd0 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir @@ -50,7 +50,7 @@ ... --- name: _Z2k1i -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir index 4da537bed6b..9cb4a6364b1 100644 --- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir +++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir @@ -69,7 +69,7 @@ ... --- name: test -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir index d1bebbfd1fd..45807b2e48b 100644 --- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir +++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir @@ -9,7 +9,7 @@ # CHECK: jrc16 $ra # encoding: [0x47,0xe3] --- name: a -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir index e7a2edbec95..d864cfa4e32 100644 --- a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir +++ b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir @@ -20,7 +20,7 @@ ... --- name: g -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -66,7 +66,7 @@ body: | ... --- name: g2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -118,7 +118,7 @@ body: | # CHECK: c: 60 25 90 03 swr $1, 3($5) # CHECK-LABEL: g2: -# CHECK: 12: 60 24 64 00 lwle $1, 0($4) -# CHECK: 16: 60 24 66 03 lwre $1, 3($4) -# CHECK: 1a: 60 25 a0 00 swle $1, 0($5) -# CHECK: 1e: 60 25 a2 03 swre $1, 3($5) +# CHECK: 14: 60 24 64 00 lwle $1, 0($4) +# CHECK: 18: 60 24 66 03 lwre $1, 3($4) +# CHECK: 1c: 60 25 a0 00 swle $1, 0($5) +# CHECK: 20: 60 25 a2 03 swre $1, 3($5) diff --git a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir index ca08b68b1c1..df7740c9291 100644 --- a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir +++ b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir @@ -41,7 +41,7 @@ ... --- name: test -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir index 5ea1341f487..517f4c2c188 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -42,7 +42,7 @@ ... --- name: mm_update_next_owner -alignment: 4 +alignment: 16 exposesReturnsTwice: false tracksRegLiveness: true liveins: diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir index c7ffce24611..e44dcef3189 100644 --- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -24,7 +24,7 @@ ... --- name: test1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false tracksRegLiveness: true frameInfo: diff --git a/llvm/test/CodeGen/PowerPC/block-placement-1.mir b/llvm/test/CodeGen/PowerPC/block-placement-1.mir index 01967e46da9..1f9b666124c 100644 --- a/llvm/test/CodeGen/PowerPC/block-placement-1.mir +++ b/llvm/test/CodeGen/PowerPC/block-placement-1.mir @@ -113,7 +113,7 @@ ... --- name: _Z6calleev -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -159,7 +159,7 @@ body: | ... --- name: _Z14TestSinglePredv -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/block-placement.mir b/llvm/test/CodeGen/PowerPC/block-placement.mir index 0566d4d4ca7..54bd9b8e923 100644 --- a/llvm/test/CodeGen/PowerPC/block-placement.mir +++ b/llvm/test/CodeGen/PowerPC/block-placement.mir @@ -82,7 +82,7 @@ ... --- name: _ZN11xercesc_2_79HashXMLCh6equalsEPKvS2_ -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/collapse-rotates.mir b/llvm/test/CodeGen/PowerPC/collapse-rotates.mir index 116f74bd46e..938b27f19d5 100644 --- a/llvm/test/CodeGen/PowerPC/collapse-rotates.mir +++ b/llvm/test/CodeGen/PowerPC/collapse-rotates.mir @@ -14,7 +14,7 @@ ... --- name: test -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir index d5e588dc0d1..70a7975aa74 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir @@ -80,7 +80,7 @@ ... --- name: unsafeAddR0R3 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -134,7 +134,7 @@ body: | ... --- name: unsafeAddR3R0 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -188,7 +188,7 @@ body: | ... --- name: safeAddR0R3 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -241,7 +241,7 @@ body: | ... --- name: safeAddR3R0 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -294,7 +294,7 @@ body: | ... --- name: unsafeLDXR3R0 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -342,7 +342,7 @@ body: | ... --- name: safeLDXZeroR3 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -389,7 +389,7 @@ body: | ... --- name: safeLDXR3R0 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir index 7597bc9ad8e..a0c461f9beb 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir @@ -213,7 +213,7 @@ --- name: testRLWNM # CHECK-ALL: name: testRLWNM -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -265,7 +265,7 @@ body: | --- name: testRLWNM8 # CHECK-ALL: name: testRLWNM8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -313,7 +313,7 @@ body: | --- name: testRLWNMo # CHECK-ALL: name: testRLWNMo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -377,7 +377,7 @@ body: | --- name: testRLWNM8o # CHECK-ALL: name: testRLWNM8o -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -436,7 +436,7 @@ body: | --- name: testSLW # CHECK-ALL: name: testSLW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -493,7 +493,7 @@ body: | --- name: testSLWo # CHECK-ALL: name: testSLWo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -556,7 +556,7 @@ body: | --- name: testSRW # CHECK-ALL: name: testSRW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -613,7 +613,7 @@ body: | --- name: testSRWo # CHECK-ALL: name: testSRWo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -676,7 +676,7 @@ body: | --- name: testSRAW # CHECK-ALL: name: testSRAW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -732,7 +732,7 @@ body: | --- name: testSRAWo # CHECK-ALL: name: testSRAWo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -791,7 +791,7 @@ body: | --- name: testRLDCL # CHECK-ALL: name: testRLDCL -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -844,7 +844,7 @@ body: | --- name: testRLDCLo # CHECK-ALL: name: testRLDCLo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -901,7 +901,7 @@ body: | --- name: testRLDCR # CHECK-ALL: name: testRLDCR -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -954,7 +954,7 @@ body: | --- name: testRLDCRo # CHECK-ALL: name: testRLDCRo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1011,7 +1011,7 @@ body: | --- name: testSLD # CHECK-ALL: name: testSLD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1062,7 +1062,7 @@ body: | --- name: testSLDo # CHECK-ALL: name: testSLDo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1117,7 +1117,7 @@ body: | --- name: testSRD # CHECK-ALL: name: testSRD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1168,7 +1168,7 @@ body: | --- name: testSRDo # CHECK-ALL: name: testSRDo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1223,7 +1223,7 @@ body: | --- name: testSRAD # CHECK-ALL: name: testSRAD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1274,7 +1274,7 @@ body: | --- name: testSRADo # CHECK-ALL: name: testSRADo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir index a59c8ff8ebe..3401a421085 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir @@ -1004,7 +1004,7 @@ --- name: testADD4 # CHECK-ALL: name: testADD4 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1063,7 +1063,7 @@ body: | --- name: testADD8 # CHECK-ALL: name: testADD8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1116,7 +1116,7 @@ body: | --- name: testADDC # CHECK-ALL: name: testADDC -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1180,7 +1180,7 @@ body: | --- name: testADDC8 # CHECK-ALL: name: testADDC8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1238,7 +1238,7 @@ body: | --- name: testADDCo # CHECK-ALL: name: testADDCo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1299,7 +1299,7 @@ body: | --- name: testADDI # CHECK-ALL: name: testADDI -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1349,7 +1349,7 @@ body: | --- name: testADDI8 # CHECK-ALL: name: testADDI8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1399,7 +1399,7 @@ body: | --- name: testANDo # CHECK-ALL: name: testANDo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1456,7 +1456,7 @@ body: | --- name: testAND8o # CHECK-ALL: name: testAND8o -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1509,7 +1509,7 @@ body: | --- name: testCMPD # CHECK-ALL: name: testCMPD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1563,7 +1563,7 @@ body: | --- name: testCMPDI # CHECK-ALL: name: testCMPDI -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1616,7 +1616,7 @@ body: | --- name: testCMPDI_F # CHECK-ALL: name: testCMPDI_F -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1669,7 +1669,7 @@ body: | --- name: testCMPLD # CHECK-ALL: name: testCMPLD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1723,7 +1723,7 @@ body: | --- name: testCMPLDI # CHECK-ALL: name: testCMPLDI -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1776,7 +1776,7 @@ body: | --- name: testCMPW # CHECK-ALL: name: testCMPW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1835,7 +1835,7 @@ body: | --- name: testCMPWI # CHECK-ALL: name: testCMPWI -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1894,7 +1894,7 @@ body: | --- name: testCMPLW # CHECK-ALL: name: testCMPLW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -1958,7 +1958,7 @@ body: | --- name: testCMPLWI # CHECK-ALL: name: testCMPLWI -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2021,7 +2021,7 @@ body: | --- name: testLBZUX # CHECK-ALL: name: testLBZUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2099,7 +2099,7 @@ body: | --- name: testLBZX # CHECK-ALL: name: testLBZX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2178,7 +2178,7 @@ body: | --- name: testLHZUX # CHECK-ALL: name: testLHZUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2256,7 +2256,7 @@ body: | --- name: testLHZX # CHECK-ALL: name: testLHZX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2333,7 +2333,7 @@ body: | --- name: testLHAUX # CHECK-ALL: name: testLHAUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2411,7 +2411,7 @@ body: | --- name: testLHAX # CHECK-ALL: name: testLHAX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2490,7 +2490,7 @@ body: | --- name: testLWZUX # CHECK-ALL: name: testLWZUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2571,7 +2571,7 @@ body: | --- name: testLWZX # CHECK-ALL: name: testLWZX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2650,7 +2650,7 @@ body: | --- name: testLWAX # CHECK-ALL: name: testLWAX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2723,7 +2723,7 @@ body: | --- name: testLDUX # CHECK-ALL: name: testLDUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2798,7 +2798,7 @@ body: | --- name: testLDX # CHECK-ALL: name: testLDX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2871,7 +2871,7 @@ body: | --- name: testLFDUX # CHECK-ALL: name: testLFDUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -2946,7 +2946,7 @@ body: | --- name: testLFDX # CHECK-ALL: name: testLFDX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3019,7 +3019,7 @@ body: | --- name: testLFSUX # CHECK-ALL: name: testLFSUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3136,7 +3136,7 @@ body: | --- name: testLFSX # CHECK-ALL: name: testLFSX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3209,7 +3209,7 @@ body: | --- name: testLXSDX # CHECK-ALL: name: testLXSDX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3282,7 +3282,7 @@ body: | --- name: testLXSSPX # CHECK-ALL: name: testLXSSPX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3355,7 +3355,7 @@ body: | --- name: testLXVX # CHECK-ALL: name: testLXVX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3428,7 +3428,7 @@ body: | --- name: testOR # CHECK-ALL: name: testOR -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3479,7 +3479,7 @@ body: | --- name: testOR8 # CHECK-ALL: name: testOR8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3528,7 +3528,7 @@ body: | --- name: testORI # CHECK-ALL: name: testORI -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3574,7 +3574,7 @@ body: | --- name: testORI8 # CHECK-ALL: name: testORI8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3620,7 +3620,7 @@ body: | --- name: testRLDCL # CHECK-ALL: name: testRLDCL -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3673,7 +3673,7 @@ body: | --- name: testRLDCLo # CHECK-ALL: name: testRLDCLo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3730,7 +3730,7 @@ body: | --- name: testRLDCR # CHECK-ALL: name: testRLDCR -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3783,7 +3783,7 @@ body: | --- name: testRLDCRo # CHECK-ALL: name: testRLDCRo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3840,7 +3840,7 @@ body: | --- name: testRLDICL # CHECK-ALL: name: testRLDICL -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3886,7 +3886,7 @@ body: | --- name: testRLDICLo # CHECK-ALL: name: testRLDICLo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3940,7 +3940,7 @@ body: | --- name: testRLDICLo2 # CHECK-ALL: name: testRLDICLo2 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -3994,7 +3994,7 @@ body: | --- name: testRLDICLo3 # CHECK-ALL: name: testRLDICLo3 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4048,7 +4048,7 @@ body: | --- name: testRLWINM # CHECK-ALL: name: testRLWINM -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4100,7 +4100,7 @@ body: | --- name: testRLWINMFullReg # CHECK-ALL: name: testRLWINMFullReg -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4152,7 +4152,7 @@ body: | --- name: testRLWINMFullRegOutOfRange # CHECK-ALL: name: testRLWINMFullRegOutOfRange -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4204,7 +4204,7 @@ body: | --- name: testRLWINM8 # CHECK-ALL: name: testRLWINM8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4250,7 +4250,7 @@ body: | --- name: testRLWINMo # CHECK-ALL: name: testRLWINMo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4315,7 +4315,7 @@ body: | --- name: testRLWINMo2 # CHECK-ALL: name: testRLWINMo2 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4379,7 +4379,7 @@ body: | --- name: testRLWINM8o # CHECK-ALL: name: testRLWINM8o -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4439,7 +4439,7 @@ body: | --- name: testSLD # CHECK-ALL: name: testSLD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4490,7 +4490,7 @@ body: | --- name: testSLDo # CHECK-ALL: name: testSLDo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4545,7 +4545,7 @@ body: | --- name: testSRD # CHECK-ALL: name: testSRD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4596,7 +4596,7 @@ body: | --- name: testSRDo # CHECK-ALL: name: testSRDo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4651,7 +4651,7 @@ body: | --- name: testSLW # CHECK-ALL: name: testSLW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4708,7 +4708,7 @@ body: | --- name: testSLWo # CHECK-ALL: name: testSLWo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4771,7 +4771,7 @@ body: | --- name: testSRW # CHECK-ALL: name: testSRW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4828,7 +4828,7 @@ body: | --- name: testSRWo # CHECK-ALL: name: testSRWo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4891,7 +4891,7 @@ body: | --- name: testSRAW # CHECK-ALL: name: testSRAW -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -4946,7 +4946,7 @@ body: | --- name: testSRAWo # CHECK-ALL: name: testSRAWo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5005,7 +5005,7 @@ body: | --- name: testSRAD # CHECK-ALL: name: testSRAD -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5056,7 +5056,7 @@ body: | --- name: testSRADo # CHECK-ALL: name: testSRADo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5111,7 +5111,7 @@ body: | --- name: testSTBUX # CHECK-ALL: name: testSTBUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5186,7 +5186,7 @@ body: | --- name: testSTBX # CHECK-ALL: name: testSTBX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5259,7 +5259,7 @@ body: | --- name: testSTHUX # CHECK-ALL: name: testSTHUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5334,7 +5334,7 @@ body: | --- name: testSTHX # CHECK-ALL: name: testSTHX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5407,7 +5407,7 @@ body: | --- name: testSTWUX # CHECK-ALL: name: testSTWUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5482,7 +5482,7 @@ body: | --- name: testSTWX # CHECK-ALL: name: testSTWX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5555,7 +5555,7 @@ body: | --- name: testSTDUX # CHECK-ALL: name: testSTDUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5628,7 +5628,7 @@ body: | --- name: testSTDX # CHECK-ALL: name: testSTDX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5699,7 +5699,7 @@ body: | --- name: testSTFSX # CHECK-ALL: name: testSTFSX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5770,7 +5770,7 @@ body: | --- name: testSTFSUX # CHECK-ALL: name: testSTFSUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5843,7 +5843,7 @@ body: | --- name: testSTFDX # CHECK-ALL: name: testSTFDX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5914,7 +5914,7 @@ body: | --- name: testSTFDUX # CHECK-ALL: name: testSTFDUX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -5987,7 +5987,7 @@ body: | --- name: testSTXSSPX # CHECK-ALL: name: testSTXSSPX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6039,7 +6039,7 @@ body: | --- name: testSTXSDX # CHECK-ALL: name: testSTXSDX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6091,7 +6091,7 @@ body: | --- name: testSTXVX # CHECK-ALL: name: testSTXVX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6143,7 +6143,7 @@ body: | --- name: testSUBFC # CHECK-ALL: name: testSUBFC -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6207,7 +6207,7 @@ body: | --- name: testSUBFC8 # CHECK-ALL: name: testSUBFC8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6265,7 +6265,7 @@ body: | --- name: testXOR # CHECK-ALL: name: testXOR -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6316,7 +6316,7 @@ body: | --- name: testXOR8 # CHECK-ALL: name: testXOR8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6365,7 +6365,7 @@ body: | --- name: testXORI # CHECK-ALL: name: testXORI -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -6411,7 +6411,7 @@ body: | --- name: testXOR8I # CHECK-ALL: name: testXOR8I -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir index be3e8e39ef4..ab7b698d630 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir @@ -3,7 +3,7 @@ --- name: testLXSSPX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -102,7 +102,7 @@ body: | --- name: testSTXSSPX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -133,7 +133,7 @@ body: | --- name: testSTXSDX -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-1.mir b/llvm/test/CodeGen/PowerPC/expand-isel-1.mir index 9577aed74cc..35e53980705 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-1.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-1.mir @@ -15,7 +15,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-10.mir b/llvm/test/CodeGen/PowerPC/expand-isel-10.mir index 5f7e2a131ab..6d51246336c 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-10.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-10.mir @@ -16,7 +16,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-2.mir b/llvm/test/CodeGen/PowerPC/expand-isel-2.mir index 2ad3a84c495..a4265e07f81 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-2.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-2.mir @@ -15,7 +15,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-3.mir b/llvm/test/CodeGen/PowerPC/expand-isel-3.mir index 924ac19744e..28273602f91 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-3.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-3.mir @@ -15,7 +15,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-4.mir b/llvm/test/CodeGen/PowerPC/expand-isel-4.mir index e552bc18911..d4484f6d527 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-4.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-4.mir @@ -16,7 +16,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-5.mir b/llvm/test/CodeGen/PowerPC/expand-isel-5.mir index 352d5e0f8cc..4142ef0fe89 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-5.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-5.mir @@ -15,7 +15,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-6.mir b/llvm/test/CodeGen/PowerPC/expand-isel-6.mir index e0fe66e5d85..9ab511e6959 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-6.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-6.mir @@ -16,7 +16,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-7.mir b/llvm/test/CodeGen/PowerPC/expand-isel-7.mir index 2540b056503..64c26247000 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-7.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-7.mir @@ -15,7 +15,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-8.mir b/llvm/test/CodeGen/PowerPC/expand-isel-8.mir index 719e8be8912..1799676afee 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-8.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-8.mir @@ -15,7 +15,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-9.mir b/llvm/test/CodeGen/PowerPC/expand-isel-9.mir index 0960a8d6716..2f0cdca8496 100644 --- a/llvm/test/CodeGen/PowerPC/expand-isel-9.mir +++ b/llvm/test/CodeGen/PowerPC/expand-isel-9.mir @@ -16,7 +16,7 @@ ... --- name: testExpandISEL -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir index 22aabf07c2f..f55a3161aae 100644 --- a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -37,7 +37,7 @@ ... --- name: main -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir index 1235c10a99d..3d6d21565e9 100644 --- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -30,7 +30,7 @@ ... --- name: fn1 -alignment: 2 +alignment: 4 exposesReturnsTwice: false tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir index 91694711604..e5e94a321c1 100644 --- a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir +++ b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir @@ -46,7 +46,7 @@ ... --- name: copycrunset -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir b/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir index 9a70ce31785..28faace4911 100644 --- a/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir +++ b/llvm/test/CodeGen/PowerPC/remove-implicit-use.mir @@ -26,7 +26,7 @@ ... --- name: test -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir index e3a7eac3407..02db2caa1e7 100644 --- a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir +++ b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir @@ -3,7 +3,7 @@ --- name: t1 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -25,7 +25,7 @@ body: | ... --- name: t2 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -53,7 +53,7 @@ body: | ... --- name: t3 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -75,7 +75,7 @@ body: | ... --- name: t4 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -100,7 +100,7 @@ body: | ... --- name: t5 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -124,7 +124,7 @@ body: | ... --- name: t6 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -153,7 +153,7 @@ body: | ... --- name: t7 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -174,7 +174,7 @@ body: | ... --- name: t8 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -194,7 +194,7 @@ body: | ... --- name: t9 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -239,7 +239,7 @@ body: | ... --- name: t10 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -262,7 +262,7 @@ body: | ... --- name: LIS8 -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -284,7 +284,7 @@ body: | ... --- name: LIS -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -306,7 +306,7 @@ body: | ... --- name: modify_and_kill_the_reg_in_the_same_inst -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | @@ -323,7 +323,7 @@ body: | ... --- name: dead_load_immediate_followed_by_a_redundancy -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/PowerPC/remove-self-copies.mir b/llvm/test/CodeGen/PowerPC/remove-self-copies.mir index d423d85527b..b5713a9349f 100644 --- a/llvm/test/CodeGen/PowerPC/remove-self-copies.mir +++ b/llvm/test/CodeGen/PowerPC/remove-self-copies.mir @@ -37,7 +37,7 @@ ... --- name: test -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir index b921bf3a957..95ee0a5e027 100644 --- a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir +++ b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir @@ -74,7 +74,7 @@ name: testRLWINMSingleUseDef # CHECK: testRLWINMSingleUseDef # CHECK-LATE: testRLWINMSingleUseDef -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -134,7 +134,7 @@ body: | ... --- name: testRLWINMNoGPRUseZero -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -194,7 +194,7 @@ body: | ... --- name: testRLWINMNoGPRUseNonZero -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -254,7 +254,7 @@ body: | ... --- name: testRLDICLSingleUseDef -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -308,7 +308,7 @@ body: | ... --- name: testRLDICLNoGPRUseZero -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -362,7 +362,7 @@ body: | ... --- name: testRLDICLNoGPRUseNonZero -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir b/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir index f9820062cfd..56212872b83 100644 --- a/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir +++ b/llvm/test/CodeGen/PowerPC/schedule-addi-load.mir @@ -29,7 +29,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc.mir b/llvm/test/CodeGen/PowerPC/setcr_bc.mir index 19b5dc1426b..3ef87237b03 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc.mir @@ -38,7 +38,7 @@ ... --- name: func -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc2.mir b/llvm/test/CodeGen/PowerPC/setcr_bc2.mir index 463186f75ec..f7214917c01 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc2.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc2.mir @@ -38,7 +38,7 @@ ... --- name: func -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc3.mir b/llvm/test/CodeGen/PowerPC/setcr_bc3.mir index a0111c0d6d2..ed05c487943 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc3.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc3.mir @@ -11,7 +11,7 @@ ... --- name: func -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/shrink-wrap.mir b/llvm/test/CodeGen/PowerPC/shrink-wrap.mir index 6715d62b9c3..cb125abde53 100644 --- a/llvm/test/CodeGen/PowerPC/shrink-wrap.mir +++ b/llvm/test/CodeGen/PowerPC/shrink-wrap.mir @@ -43,7 +43,7 @@ ... --- name: shrinkwrapme -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir index 49c645f50f0..b26e50f5be6 100644 --- a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir +++ b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir @@ -16,7 +16,7 @@ ... --- name: tls_func -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir index 660fb2c43b9..d25a5b07a33 100644 --- a/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir +++ b/llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir @@ -16,7 +16,7 @@ ... --- name: tls_func -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir b/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir index f3a5f407acc..d93758344f9 100644 --- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir +++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.mir @@ -20,7 +20,7 @@ # in the middle. Because the non-select depends on the result of a previous # select, we cannot optimize the sequence to share control-flow. name: cmov_interleaved_bad -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gpr } @@ -106,7 +106,7 @@ body: | # the tail basic block, while debug info associated with non-selects is left # in the head basic block. name: cmov_interleaved_debug_value -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gpr } diff --git a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir index dfb86c028eb..88a767d0788 100644 --- a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir +++ b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir @@ -23,7 +23,7 @@ # CHECK: id: 114, class --- name: autogen_SD21418 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: vr128bit } diff --git a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir index 1dcf96298d5..32fad11f1d3 100644 --- a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir +++ b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir @@ -22,7 +22,7 @@ define void @encode_one_macroblock() { ret void } --- name: encode_one_macroblock -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: addr64bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-04.mir b/llvm/test/CodeGen/SystemZ/cond-move-04.mir index 5651c6bdc1e..6e6bd061d53 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-04.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-04.mir @@ -37,7 +37,7 @@ --- name: fun -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gr32bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-05.mir b/llvm/test/CodeGen/SystemZ/cond-move-05.mir index de33f49734f..60035746c7f 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-05.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-05.mir @@ -47,7 +47,7 @@ --- name: main -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: gr64bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-08.mir b/llvm/test/CodeGen/SystemZ/cond-move-08.mir index aa5c4cd1697..5808fc643bc 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-08.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-08.mir @@ -83,7 +83,7 @@ --- name: fun1 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: grx32bit } diff --git a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir index fa0b3ee8012..f987b80e9fa 100644 --- a/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir +++ b/llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir @@ -117,7 +117,7 @@ --- name: fun -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64bit } diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-00.mir b/llvm/test/CodeGen/SystemZ/debuginstr-00.mir index 53a43d03a22..25cda188689 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-00.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-00.mir @@ -52,7 +52,7 @@ ... --- name: put_charge_groups_in_box -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: maxCallFrameSize: 0 diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-01.mir b/llvm/test/CodeGen/SystemZ/debuginstr-01.mir index bcc7f547941..162bc6df757 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-01.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-01.mir @@ -50,7 +50,7 @@ ... --- name: f1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r2d' } diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-02.mir b/llvm/test/CodeGen/SystemZ/debuginstr-02.mir index 1a209496d03..7c4f6735cf5 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-02.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-02.mir @@ -47,7 +47,7 @@ ... --- name: fun -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32bit } diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir b/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir index 8d76c33f8ff..f61ca330073 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir @@ -166,6 +166,6 @@ ... --- name: Fun -alignment: 4 +alignment: 16 tracksRegLiveness: true ... diff --git a/llvm/test/CodeGen/SystemZ/fp-conv-17.mir b/llvm/test/CodeGen/SystemZ/fp-conv-17.mir index 4cde00ee9d1..42c5e99a230 100644 --- a/llvm/test/CodeGen/SystemZ/fp-conv-17.mir +++ b/llvm/test/CodeGen/SystemZ/fp-conv-17.mir @@ -81,7 +81,7 @@ --- name: f0 -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: addr64bit } diff --git a/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir b/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir index 707e7c538fd..f36216e61a2 100644 --- a/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir +++ b/llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir @@ -88,7 +88,7 @@ --- name: proofnumberscan -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: addr64bit } diff --git a/llvm/test/CodeGen/SystemZ/misched-readadvances.mir b/llvm/test/CodeGen/SystemZ/misched-readadvances.mir index df8ca2f5f95..12dea8b8f25 100644 --- a/llvm/test/CodeGen/SystemZ/misched-readadvances.mir +++ b/llvm/test/CodeGen/SystemZ/misched-readadvances.mir @@ -16,7 +16,7 @@ --- name: Perl_do_sv_dump -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0 : diff --git a/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir b/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir index 43b9a1b8a13..c3ebec18424 100644 --- a/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir +++ b/llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir @@ -55,7 +55,7 @@ ... --- name: LearnStoreTT -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r2d' } diff --git a/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir b/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir index 65758bea4fd..e6a1e7e50cb 100644 --- a/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir +++ b/llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir @@ -27,7 +27,7 @@ ... --- name: main -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: grx32bit } diff --git a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir index 195dbb996ef..cf2c274b1c3 100644 --- a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir +++ b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir @@ -11,7 +11,7 @@ # PR33677 --- name: main -alignment: 2 +alignment: 4 tracksRegLiveness: true # CHECK: $r0l = COPY renamable $r1l # Although R0L partially redefines R0Q, it must not mark R0Q as kill diff --git a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir index 4245dafb00d..86e22ad3644 100644 --- a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir +++ b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir @@ -17,7 +17,7 @@ # PR40215. --- name: main -alignment: 4 +alignment: 16 tracksRegLiveness: true machineFunctionInfo: {} body: | diff --git a/llvm/test/CodeGen/SystemZ/subregliveness-06.mir b/llvm/test/CodeGen/SystemZ/subregliveness-06.mir index d0dc1652c15..96aa9109a51 100644 --- a/llvm/test/CodeGen/SystemZ/subregliveness-06.mir +++ b/llvm/test/CodeGen/SystemZ/subregliveness-06.mir @@ -144,7 +144,7 @@ ... --- name: func_32 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r2d', virtual-reg: '%10' } diff --git a/llvm/test/CodeGen/SystemZ/subregliveness-07.mir b/llvm/test/CodeGen/SystemZ/subregliveness-07.mir index 599e5a5e10f..e8f951ea2a1 100644 --- a/llvm/test/CodeGen/SystemZ/subregliveness-07.mir +++ b/llvm/test/CodeGen/SystemZ/subregliveness-07.mir @@ -18,7 +18,7 @@ --- name: main -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/Thumb/PR36658.mir b/llvm/test/CodeGen/Thumb/PR36658.mir index d6ec0ba370b..3c988597b93 100644 --- a/llvm/test/CodeGen/Thumb/PR36658.mir +++ b/llvm/test/CodeGen/Thumb/PR36658.mir @@ -131,7 +131,7 @@ ... --- name: foo4 -alignment: 1 +alignment: 2 tracksRegLiveness: true liveins: - { reg: '$r0' } diff --git a/llvm/test/CodeGen/Thumb/tbb-reuse.mir b/llvm/test/CodeGen/Thumb/tbb-reuse.mir index d079e53615b..5eb40dc0983 100644 --- a/llvm/test/CodeGen/Thumb/tbb-reuse.mir +++ b/llvm/test/CodeGen/Thumb/tbb-reuse.mir @@ -56,7 +56,7 @@ ... --- name: jump_table -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir index 9ddfda63209..1efe18e129c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir @@ -38,7 +38,7 @@ ... --- name: do_copy -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir index 4d638a96de2..2b12ec14901 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir @@ -57,7 +57,7 @@ ... --- name: size_limit -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir index b3a69b57ed5..92bd7344dfa 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir @@ -66,7 +66,7 @@ ... --- name: massive -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir index 7033ddb0285..bc5f88acfc6 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir @@ -59,7 +59,7 @@ ... --- name: size_limit -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir index 6e89662080f..3ea75a295f6 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir @@ -51,7 +51,7 @@ ... --- name: skip_spill -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir index ca1fb2df8b1..b69d35859a7 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-read.mir @@ -40,7 +40,7 @@ ... --- name: mov_between_dec_end -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir index e66c73b96ce..97ac75de497 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-spill.mir @@ -46,7 +46,7 @@ ... --- name: skip_spill -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir index ebf077c504c..2d31c8ad63b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir @@ -40,7 +40,7 @@ ... --- name: mov_between_dec_end -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir index ebb93ecd05a..54973cc683b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir @@ -102,7 +102,7 @@ ... --- name: header_not_target_unrolled_loop -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir index 4bd7754ad64..bcd80c70bb4 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir @@ -61,7 +61,7 @@ ... --- name: non_loop -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir index 44ce736a082..754d35ea89b 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir @@ -61,7 +61,7 @@ ... --- name: ne_trip_count -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir index 92b5c75d2d4..69a5bd33a96 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -54,7 +54,7 @@ ... --- name: size_limit -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir index 742f67ae341..9d86f9291aa 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir @@ -60,7 +60,7 @@ ... --- name: search -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir index c32303bc681..9195b977224 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir @@ -59,7 +59,7 @@ ... --- name: size_limit -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir index 8839bfbe4d2..e05adc6b474 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir @@ -61,7 +61,7 @@ ... --- name: copy -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/m4-sched-ldr.mir b/llvm/test/CodeGen/Thumb2/m4-sched-ldr.mir index 41abefd85a6..8212db6d4e1 100644 --- a/llvm/test/CodeGen/Thumb2/m4-sched-ldr.mir +++ b/llvm/test/CodeGen/Thumb2/m4-sched-ldr.mir @@ -25,7 +25,7 @@ ... --- name: test -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block.mir index 61f319002cc..6c9da8f854a 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block.mir @@ -22,7 +22,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir index 4a711ddc82d..ae70ed83366 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir @@ -24,7 +24,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir index 319846942f4..c23f6abe67c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir @@ -25,7 +25,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir index c70dd4cce46..6b8d471d9ba 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir @@ -26,7 +26,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir index 533de9232fc..245e604ef15 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir @@ -24,7 +24,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir index a914bc2ed25..7ff04eb700f 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir @@ -23,7 +23,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir index fd39cbecf14..765e054118c 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir @@ -26,7 +26,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir index dc29bcab71a..13878923ab5 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir @@ -24,7 +24,7 @@ ... --- name: test_vminnmq_m_f32_v2 -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir index fc14030f998..037e8657126 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir @@ -49,7 +49,7 @@ ... --- name: vpnot -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$q0', virtual-reg: '' } @@ -83,7 +83,7 @@ body: | ... --- name: vpnot_end -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$q0', virtual-reg: '' } @@ -125,7 +125,7 @@ body: | ... --- name: vpnot_two -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$q0', virtual-reg: '' } @@ -161,7 +161,7 @@ body: | ... --- name: vpnot_lots -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$q0', virtual-reg: '' } @@ -203,7 +203,7 @@ body: | ... --- name: vpnot_first -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$q0', virtual-reg: '' } @@ -234,7 +234,7 @@ body: | ... --- name: vpnot_many -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$q0', virtual-reg: '' } diff --git a/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir b/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir index ab565db3435..e49559fffc6 100644 --- a/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir +++ b/llvm/test/CodeGen/Thumb2/tbb-removeadd.mir @@ -37,7 +37,7 @@ ... --- name: Func -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir index b4afd808ac1..31f1da5c674 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir @@ -9,7 +9,7 @@ ... --- name: test_check_type -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir index e0e1c2d3ca8..28ed57dcdf8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir @@ -24,7 +24,7 @@ ... --- name: test_add_v16i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -50,7 +50,7 @@ body: | ... --- name: test_add_v8i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -76,7 +76,7 @@ body: | ... --- name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -102,7 +102,7 @@ body: | ... --- name: test_add_v2i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir index 59b0b14d585..98b38514b7e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir @@ -27,7 +27,7 @@ ... --- name: test_add_v32i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -72,7 +72,7 @@ body: | ... --- name: test_add_v16i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -117,7 +117,7 @@ body: | ... --- name: test_add_v8i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -162,7 +162,7 @@ body: | ... --- name: test_add_v4i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir index 4120ed5ce6f..2aece951268 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir @@ -31,7 +31,7 @@ ... --- name: test_add_v64i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -78,7 +78,7 @@ body: | ... --- name: test_add_v32i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -125,7 +125,7 @@ body: | ... --- name: test_add_v16i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -168,7 +168,7 @@ body: | ... --- name: test_add_v8i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -211,7 +211,7 @@ body: | ... --- name: test_add_v64i8_2 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir index f3f5d4cdac7..69c7dd4cb72 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir @@ -15,7 +15,7 @@ --- name: test_add_i1 # CHECK-LABEL: name: test_add_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_add_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_add_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir index abde7a28c14..1f09e4639df 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir @@ -30,7 +30,7 @@ ... --- name: test_and_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -57,7 +57,7 @@ body: | ... --- name: test_and_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -82,7 +82,7 @@ body: | ... --- name: test_and_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -107,7 +107,7 @@ body: | ... --- name: test_and_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -132,7 +132,7 @@ body: | ... --- name: test_and_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir index eece3021c5e..0964e06d2b7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir @@ -7,7 +7,7 @@ ... --- name: test_ashr -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: test_ashr_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir index 2cf3eba8ceb..4e11683a07c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir @@ -18,7 +18,7 @@ --- name: test # ALL-LABEL: name: test -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir index 055ff77f1da..442fb2ffbbb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir @@ -35,7 +35,7 @@ ... --- name: test_cmp_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -64,7 +64,7 @@ body: | ... --- name: test_cmp_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -93,7 +93,7 @@ body: | ... --- name: test_cmp_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -122,7 +122,7 @@ body: | ... --- name: test_cmp_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -151,7 +151,7 @@ body: | ... --- name: test_cmp_p0 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir index aafedd3b5b7..c891608d60a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir @@ -64,7 +64,7 @@ ... --- name: test_sext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -94,7 +94,7 @@ body: | ... --- name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -117,7 +117,7 @@ body: | ... --- name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -140,7 +140,7 @@ body: | ... --- name: test_sext_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -163,7 +163,7 @@ body: | ... --- name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -190,7 +190,7 @@ body: | ... --- name: test_zext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -213,7 +213,7 @@ body: | ... --- name: test_zext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -236,7 +236,7 @@ body: | ... --- name: test_zext_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -259,7 +259,7 @@ body: | ... --- name: test_anyext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -284,7 +284,7 @@ body: | ... --- name: test_anyext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -307,7 +307,7 @@ body: | ... --- name: test_anyext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -330,7 +330,7 @@ body: | ... --- name: test_anyext_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir index 71f1facfb81..aafba4119bb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir @@ -92,7 +92,7 @@ ... --- name: test_zext_i1toi8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -126,7 +126,7 @@ body: | ... --- name: test_zext_i1toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -159,7 +159,7 @@ body: | ... --- name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -193,7 +193,7 @@ body: | ... --- name: test_zext_i8toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -221,7 +221,7 @@ body: | ... --- name: test_zext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -249,7 +249,7 @@ body: | ... --- name: test_zext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -277,7 +277,7 @@ body: | ... --- name: test_sext_i1toi8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -303,7 +303,7 @@ body: | ... --- name: test_sext_i1toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -329,7 +329,7 @@ body: | ... --- name: test_sext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -356,7 +356,7 @@ body: | ... --- name: test_sext_i8toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -384,7 +384,7 @@ body: | ... --- name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -412,7 +412,7 @@ body: | ... --- name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -440,7 +440,7 @@ body: | ... --- name: test_anyext_i1toi8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -470,7 +470,7 @@ body: | ... --- name: test_anyext_i1toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -500,7 +500,7 @@ body: | ... --- name: test_anyext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -530,7 +530,7 @@ body: | ... --- name: test_anyext_i8toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -558,7 +558,7 @@ body: | ... --- name: test_anyext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -586,7 +586,7 @@ body: | ... --- name: test_anyext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir index 05e2638bfea..8142fe25d6c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fadd_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fadd_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir index cb0c685ce3e..23f3bf4796a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fdiv_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fdiv_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir index 347d56a9094..0a888ab6744 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fmul_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fmul_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir index 58786f3e53f..6c47a859876 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir @@ -11,7 +11,7 @@ ... --- name: test -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir index fbe139f9d70..057ab7c4c17 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir @@ -10,7 +10,7 @@ ... --- name: test_fptrunc -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir index 7979d92e51f..897fcf2c62a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fsub_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fsub_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir index 5486b39ab47..49fbe4bc362 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir @@ -8,7 +8,7 @@ --- name: test_insert_128 # ALL-LABEL: name: test_insert_128 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir index d6cb9d42db0..99ac3d4ab7b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir @@ -12,7 +12,7 @@ ... --- name: test_insert_128 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -38,7 +38,7 @@ body: | ... --- name: test_insert_256 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir index 8cca8361bee..fd284ebfc61 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir @@ -7,7 +7,7 @@ ... --- name: test_lshr -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: test_lshr_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir index ad1c713a87c..8e2bc5d4f28 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir @@ -3,7 +3,7 @@ --- name: test_memop_s8tos32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false body: | @@ -38,7 +38,7 @@ body: | ... --- name: test_memop_s64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false liveins: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir index c7de33ddb58..a550a823831 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir @@ -3,7 +3,7 @@ --- name: test_memop_s8tos32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false body: | @@ -38,7 +38,7 @@ body: | ... --- name: test_memop_s64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false liveins: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir index 122c45212a8..d4c753435b4 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir @@ -22,7 +22,7 @@ ... --- name: test_mul_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -52,7 +52,7 @@ body: | ... --- name: test_mul_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -78,7 +78,7 @@ body: | ... --- name: test_mul_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -104,7 +104,7 @@ body: | ... --- name: test_mul_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir index 659e3aec71f..3b8455684f3 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir @@ -22,7 +22,7 @@ --- name: test_mul_v8i16 # ALL-LABEL: name: test_mul_v8i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -52,7 +52,7 @@ body: | --- name: test_mul_v4i32 # ALL-LABEL: name: test_mul_v4i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -82,7 +82,7 @@ body: | --- name: test_mul_v2i64 # ALL-LABEL: name: test_mul_v2i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir index 175bcbca52c..4965b069715 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir @@ -22,7 +22,7 @@ --- name: test_mul_v16i16 # ALL-LABEL: name: test_mul_v16i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -52,7 +52,7 @@ body: | --- name: test_mul_v8i32 # ALL-LABEL: name: test_mul_v8i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -82,7 +82,7 @@ body: | --- name: test_mul_v4i64 # ALL-LABEL: name: test_mul_v4i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir index e7dbcb2d76c..77a94581b66 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir @@ -24,7 +24,7 @@ --- name: test_mul_v32i16 # ALL-LABEL: name: test_mul_v32i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -54,7 +54,7 @@ body: | --- name: test_mul_v16i32 # ALL-LABEL: name: test_mul_v16i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -84,7 +84,7 @@ body: | --- name: test_mul_v8i64 # ALL-LABEL: name: test_mul_v8i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir index 6da13f654f1..ee571d3430c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir @@ -30,7 +30,7 @@ ... --- name: test_or_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -60,7 +60,7 @@ body: | ... --- name: test_or_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_or_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -110,7 +110,7 @@ body: | ... --- name: test_or_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -135,7 +135,7 @@ body: | ... --- name: test_or_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir index 25ffa8c3f45..cb8c790e6c5 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir @@ -118,7 +118,7 @@ ... --- name: test_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -186,7 +186,7 @@ body: | ... --- name: test_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -250,7 +250,7 @@ body: | ... --- name: test_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -314,7 +314,7 @@ body: | ... --- name: test_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -382,7 +382,7 @@ body: | ... --- name: test_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -450,7 +450,7 @@ body: | ... --- name: test_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -517,7 +517,7 @@ body: | ... --- name: test_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir index ee4be22f95e..16ffb9510ae 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir @@ -7,7 +7,7 @@ ... --- name: test_shl -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: test_shl_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir index c5775f3901c..f6be978db09 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir @@ -24,7 +24,7 @@ ... --- name: test_sub_v16i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -49,7 +49,7 @@ body: | ... --- name: test_sub_v8i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -74,7 +74,7 @@ body: | ... --- name: test_sub_v4i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -99,7 +99,7 @@ body: | ... --- name: test_sub_v2i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir index 49a7ce5a01f..6f47c5fa08d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir @@ -25,7 +25,7 @@ ... --- name: test_sub_v32i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -50,7 +50,7 @@ body: | ... --- name: test_sub_v16i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -75,7 +75,7 @@ body: | ... --- name: test_sub_v8i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -100,7 +100,7 @@ body: | ... --- name: test_sub_v4i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir index 725299a8920..400b46e77ee 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir @@ -25,7 +25,7 @@ ... --- name: test_sub_v64i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -50,7 +50,7 @@ body: | ... --- name: test_sub_v32i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -75,7 +75,7 @@ body: | ... --- name: test_sub_v16i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -100,7 +100,7 @@ body: | ... --- name: test_sub_v8i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir index ff4af534baa..74289897b6a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir @@ -13,7 +13,7 @@ ... --- name: test_sub_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -43,7 +43,7 @@ body: | ... --- name: test_sub_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir index 13ac1e072b4..754402492b8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir @@ -30,7 +30,7 @@ ... --- name: test_xor_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_xor_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -80,7 +80,7 @@ body: | ... --- name: test_xor_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -105,7 +105,7 @@ body: | ... --- name: test_xor_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -130,7 +130,7 @@ body: | ... --- name: test_xor_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir index 98a6693645a..7ce86c93a95 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir @@ -26,7 +26,7 @@ --- name: test_mul_vec256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -49,7 +49,7 @@ body: | ... --- name: test_add_vec256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -72,7 +72,7 @@ body: | ... --- name: test_sub_vec256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -96,7 +96,7 @@ body: | --- name: test_load_v8i32_noalign # CHECK-LABEL: name: test_load_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -118,7 +118,7 @@ body: | --- name: test_store_v8i32_noalign # CHECK-LABEL: name: test_store_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir index c7c64cfe96a..7da4b0122e6 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir @@ -29,7 +29,7 @@ --- name: test_mul_vec512 # CHECK-LABEL: name: test_mul_vec512 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -49,7 +49,7 @@ body: | --- name: test_add_vec512 # CHECK-LABEL: name: test_add_vec512 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -69,7 +69,7 @@ body: | --- name: test_sub_vec512 # CHECK-LABEL: name: test_sub_vec512 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -89,7 +89,7 @@ body: | name: test_load_v16i32_noalign # CHECK-LABEL: name: test_load_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -111,7 +111,7 @@ body: | --- name: test_store_v16i32_noalign # CHECK-LABEL: name: test_store_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir index c06c2609528..cd5fa912add 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir @@ -10,7 +10,7 @@ --- name: test_uadde_i32 # CHECK-LABEL: name: test_uadde_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir index 2b730581d86..9cf6845b3a0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -463,7 +463,7 @@ ... --- name: test_add_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -499,7 +499,7 @@ body: | ... --- name: test_add_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -535,7 +535,7 @@ body: | ... --- name: test_add_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -571,7 +571,7 @@ body: | ... --- name: test_add_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -607,7 +607,7 @@ body: | ... --- name: test_mul_gpr -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -656,7 +656,7 @@ body: | ... --- name: test_add_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -704,7 +704,7 @@ body: | ... --- name: test_add_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -752,7 +752,7 @@ body: | ... --- name: test_fsub_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -795,7 +795,7 @@ body: | ... --- name: test_fmul_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -838,7 +838,7 @@ body: | ... --- name: test_fdiv_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -881,7 +881,7 @@ body: | ... --- name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -917,7 +917,7 @@ body: | ... --- name: test_add_v4f32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -953,7 +953,7 @@ body: | ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -982,7 +982,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1011,7 +1011,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1040,7 +1040,7 @@ body: | ... --- name: test_load_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: false @@ -1070,7 +1070,7 @@ body: | ... --- name: test_load_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1104,7 +1104,7 @@ body: | ... --- name: test_load_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1138,7 +1138,7 @@ body: | ... --- name: test_load_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1167,7 +1167,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1199,7 +1199,7 @@ body: | ... --- name: test_store_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1231,7 +1231,7 @@ body: | ... --- name: test_store_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1270,7 +1270,7 @@ body: | ... --- name: test_store_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1309,7 +1309,7 @@ body: | ... --- name: constInt_check -alignment: 4 +alignment: 16 legalized: true registers: - { id: 0, class: _ } @@ -1339,7 +1339,7 @@ body: | ... --- name: trunc_check -alignment: 4 +alignment: 16 legalized: true registers: - { id: 0, class: _ } @@ -1402,7 +1402,7 @@ body: | ... --- name: test_icmp_eq_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1443,7 +1443,7 @@ body: | ... --- name: test_icmp_eq_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1484,7 +1484,7 @@ body: | ... --- name: test_icmp_eq_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1519,7 +1519,7 @@ body: | ... --- name: test_icmp_eq_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1554,7 +1554,7 @@ body: | ... --- name: test_xor_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1584,7 +1584,7 @@ body: | ... --- name: test_or_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1614,7 +1614,7 @@ body: | ... --- name: test_and_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1644,7 +1644,7 @@ body: | ... --- name: test_and_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1674,7 +1674,7 @@ body: | ... --- name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1696,7 +1696,7 @@ body: | ... --- name: test_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1722,7 +1722,7 @@ body: | ... --- name: test_undef2 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1758,7 +1758,7 @@ body: | ... --- name: test_undef3 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1784,7 +1784,7 @@ body: | ... --- name: test_undef4 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1830,7 +1830,7 @@ body: | ... --- name: test_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false tracksRegLiveness: true @@ -1910,7 +1910,7 @@ body: | ... --- name: test_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false tracksRegLiveness: true @@ -1986,7 +1986,7 @@ body: | ... --- name: test_fpext -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -2020,7 +2020,7 @@ body: | ... --- name: test_fptrunc -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2077,7 +2077,7 @@ body: | ... --- name: int32_to_float -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2111,7 +2111,7 @@ body: | ... --- name: int64_to_float -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2145,7 +2145,7 @@ body: | ... --- name: int32_to_double -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2179,7 +2179,7 @@ body: | ... --- name: int64_to_double -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2213,7 +2213,7 @@ body: | ... --- name: float_to_int8 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2251,7 +2251,7 @@ body: | ... --- name: float_to_int16 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2289,7 +2289,7 @@ body: | ... --- name: float_to_int32 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2323,7 +2323,7 @@ body: | ... --- name: float_to_int64 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2357,7 +2357,7 @@ body: | ... --- name: double_to_int8 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2395,7 +2395,7 @@ body: | ... --- name: double_to_int16 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2433,7 +2433,7 @@ body: | ... --- name: double_to_int32 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2467,7 +2467,7 @@ body: | ... --- name: double_to_int64 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2501,7 +2501,7 @@ body: | ... --- name: fcmp_float_oeq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2548,7 +2548,7 @@ body: | ... --- name: fcmp_float_ogt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2595,7 +2595,7 @@ body: | ... --- name: fcmp_float_oge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2642,7 +2642,7 @@ body: | ... --- name: fcmp_float_olt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2689,7 +2689,7 @@ body: | ... --- name: fcmp_float_ole -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2736,7 +2736,7 @@ body: | ... --- name: fcmp_float_one -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2783,7 +2783,7 @@ body: | ... --- name: fcmp_float_ord -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2830,7 +2830,7 @@ body: | ... --- name: fcmp_float_uno -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2877,7 +2877,7 @@ body: | ... --- name: fcmp_float_ueq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2924,7 +2924,7 @@ body: | ... --- name: fcmp_float_ugt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2971,7 +2971,7 @@ body: | ... --- name: fcmp_float_uge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3018,7 +3018,7 @@ body: | ... --- name: fcmp_float_ult -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3065,7 +3065,7 @@ body: | ... --- name: fcmp_float_ule -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3112,7 +3112,7 @@ body: | ... --- name: fcmp_float_une -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3159,7 +3159,7 @@ body: | ... --- name: fcmp_double_oeq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3206,7 +3206,7 @@ body: | ... --- name: fcmp_double_ogt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3253,7 +3253,7 @@ body: | ... --- name: fcmp_double_oge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3300,7 +3300,7 @@ body: | ... --- name: fcmp_double_olt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3347,7 +3347,7 @@ body: | ... --- name: fcmp_double_ole -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3394,7 +3394,7 @@ body: | ... --- name: fcmp_double_one -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3441,7 +3441,7 @@ body: | ... --- name: fcmp_double_ord -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3488,7 +3488,7 @@ body: | ... --- name: fcmp_double_uno -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3535,7 +3535,7 @@ body: | ... --- name: fcmp_double_ueq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3582,7 +3582,7 @@ body: | ... --- name: fcmp_double_ugt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3629,7 +3629,7 @@ body: | ... --- name: fcmp_double_uge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3676,7 +3676,7 @@ body: | ... --- name: fcmp_double_ult -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3723,7 +3723,7 @@ body: | ... --- name: fcmp_double_ule -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3770,7 +3770,7 @@ body: | ... --- name: fcmp_double_une -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir index d4fd6e29ab3..7d61e1c3f05 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir @@ -21,7 +21,7 @@ --- name: test_global_ptrv # CHECK-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -56,7 +56,7 @@ body: | --- name: test_global_valv # CHECK-LABEL: name: test_global_valv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir index 830251e3758..ce3f0ca611b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir @@ -21,7 +21,7 @@ --- name: test_global_ptrv # CHECK-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X64ALL: registers: @@ -54,7 +54,7 @@ body: | --- name: test_global_valv # CHECK-LABEL: name: test_global_valv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X64ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir index 2584ff420e4..987f67bad15 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir @@ -28,7 +28,7 @@ --- name: test_add_v16i8 # ALL-LABEL: name: test_add_v16i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: @@ -70,7 +70,7 @@ body: | --- name: test_add_v8i16 # ALL-LABEL: name: test_add_v8i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: @@ -112,7 +112,7 @@ body: | --- name: test_add_v4i32 # ALL-LABEL: name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: @@ -154,7 +154,7 @@ body: | --- name: test_add_v2i64 # ALL-LABEL: name: test_add_v2i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir index ea6bfa57628..3ee95929441 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir @@ -26,7 +26,7 @@ --- name: test_add_v32i8 # ALL-LABEL: name: test_add_v32i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -66,7 +66,7 @@ body: | --- name: test_add_v16i16 # ALL-LABEL: name: test_add_v16i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -106,7 +106,7 @@ body: | --- name: test_add_v8i32 # ALL-LABEL: name: test_add_v8i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -146,7 +146,7 @@ body: | --- name: test_add_v4i64 # ALL-LABEL: name: test_add_v4i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir index ce858fc79e5..c5498fda126 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir @@ -27,7 +27,7 @@ ... --- name: test_add_v64i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | ... --- name: test_add_v32i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -79,7 +79,7 @@ body: | ... --- name: test_add_v16i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -105,7 +105,7 @@ body: | ... --- name: test_add_v8i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir index e48853dc7d8..773813f19cd 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir @@ -9,7 +9,7 @@ ... --- name: test_add_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add.mir index b4166a89e0a..d6e616109df 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add.mir @@ -83,7 +83,7 @@ body: | --- name: test_add_i16 # ALL-LABEL: name: test_add_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -108,7 +108,7 @@ body: | --- name: test_add_i8 # ALL-LABEL: name: test_add_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -133,7 +133,7 @@ body: | --- name: test_add_v4i32 # ALL-LABEL: name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -164,7 +164,7 @@ body: | --- name: test_add_v4f32 # ALL-LABEL: name: test_add_v4f32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir index 0f83b306b7d..d674e0b43fc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir @@ -25,7 +25,7 @@ ... --- name: test_and_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_and_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_and_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -115,7 +115,7 @@ body: | ... --- name: test_and_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir index ae051f99084..01efef5a705 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir @@ -72,7 +72,7 @@ ... --- name: test_ashr_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -108,7 +108,7 @@ body: | ... --- name: test_ashr_i64_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -139,7 +139,7 @@ body: | ... --- name: test_ashr_i64_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -170,7 +170,7 @@ body: | ... --- name: test_ashr_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -206,7 +206,7 @@ body: | ... --- name: test_ashr_i32_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -237,7 +237,7 @@ body: | ... --- name: test_ashr_i32_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -268,7 +268,7 @@ body: | ... --- name: test_ashr_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -307,7 +307,7 @@ body: | ... --- name: test_ashr_i16_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -341,7 +341,7 @@ body: | ... --- name: test_ashr_i16_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -375,7 +375,7 @@ body: | ... --- name: test_ashr_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -414,7 +414,7 @@ body: | ... --- name: test_ashr_i8_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -448,7 +448,7 @@ body: | ... --- name: test_ashr_i8_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir index 752bd03f1f2..fe58606c2e9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir @@ -10,7 +10,7 @@ --- name: test_blsi32rr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -36,7 +36,7 @@ body: | ... --- name: test_blsi32rr_nomatch -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir b/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir index d6d095e366c..b1a30fbce06 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir @@ -7,7 +7,7 @@ --- name: test_blsr32rr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -33,7 +33,7 @@ body: | ... --- name: test_blsr32rr_nomatch -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-br.mir b/llvm/test/CodeGen/X86/GlobalISel/select-br.mir index 4872fb70c95..d28fa574238 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-br.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-br.mir @@ -17,7 +17,7 @@ --- name: uncondbr # CHECK-LABEL: name: uncondbr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # CHECK: JMP_1 %bb.2 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir b/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir index 1906a00e12e..d21af414edb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir @@ -19,7 +19,7 @@ --- name: test # CHECK-LABEL: name: test -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir index ad106b000e8..2ff1fcba561 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir @@ -83,7 +83,7 @@ ... --- name: test_icmp_eq_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -114,7 +114,7 @@ body: | ... --- name: test_icmp_eq_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -145,7 +145,7 @@ body: | ... --- name: test_icmp_eq_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -176,7 +176,7 @@ body: | ... --- name: test_icmp_eq_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -207,7 +207,7 @@ body: | ... --- name: test_icmp_ne_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -238,7 +238,7 @@ body: | ... --- name: test_icmp_ugt_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -269,7 +269,7 @@ body: | ... --- name: test_icmp_uge_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -300,7 +300,7 @@ body: | ... --- name: test_icmp_ult_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -331,7 +331,7 @@ body: | ... --- name: test_icmp_ule_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -362,7 +362,7 @@ body: | ... --- name: test_icmp_sgt_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -393,7 +393,7 @@ body: | ... --- name: test_icmp_sge_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -424,7 +424,7 @@ body: | ... --- name: test_icmp_slt_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -455,7 +455,7 @@ body: | ... --- name: test_icmp_sle_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir index 08c8b67e514..33c561f8865 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir @@ -127,7 +127,7 @@ body: | ... --- name: const_i64_u32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -164,7 +164,7 @@ body: | ... --- name: main -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir index 5e36ffa6fc5..cb6948a16cb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir @@ -31,7 +31,7 @@ --- name: test_copy # ALL-LABEL: name: test_copy -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -57,7 +57,7 @@ body: | --- name: test_copy2 # ALL-LABEL: name: test_copy2 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -83,7 +83,7 @@ body: | --- name: test_copy3 # ALL-LABEL: name: test_copy3 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -113,7 +113,7 @@ body: | --- name: test_copy4 # ALL-LABEL: name: test_copy4 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -143,7 +143,7 @@ body: | --- name: test_copy5 # ALL-LABEL: name: test_copy5 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -173,7 +173,7 @@ body: | --- name: test_copy6 # ALL-LABEL: name: test_copy6 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir index 3c61ff623d8..4eb2d5b148a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -25,7 +25,7 @@ ... --- name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -51,7 +51,7 @@ body: | ... --- name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -74,7 +74,7 @@ body: | ... --- name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -97,7 +97,7 @@ body: | ... --- name: anyext_s64_from_s1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -122,7 +122,7 @@ body: | ... --- name: anyext_s64_from_s8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -148,7 +148,7 @@ body: | ... --- name: anyext_s64_from_s16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -174,7 +174,7 @@ body: | ... --- name: anyext_s64_from_s32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir index ce3e7900731..b236ba24800 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -48,7 +48,7 @@ --- name: test_zext_i1toi8 # ALL-LABEL: name: test_zext_i1toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -84,7 +84,7 @@ body: | --- name: test_zext_i1toi16 # ALL-LABEL: name: test_zext_i1toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -123,7 +123,7 @@ body: | --- name: test_zext_i1 # ALL-LABEL: name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -162,7 +162,7 @@ body: | --- name: test_zext_i8 # ALL-LABEL: name: test_zext_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -188,7 +188,7 @@ body: | --- name: test_zext_i16 # ALL-LABEL: name: test_zext_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -214,7 +214,7 @@ body: | --- name: test_sext_i8 # ALL-LABEL: name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -240,7 +240,7 @@ body: | --- name: test_sext_i16 # ALL-LABEL: name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -266,7 +266,7 @@ body: | --- name: test_anyext_i1toi8 # ALL-LABEL: name: test_anyext_i1toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -300,7 +300,7 @@ body: | --- name: test_anyext_i1toi16 # ALL-LABEL: name: test_anyext_i1toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -335,7 +335,7 @@ body: | --- name: test_anyext_i1toi32 # ALL-LABEL: name: test_anyext_i1toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -370,7 +370,7 @@ body: | --- name: test_anyext_i8toi16 # ALL-LABEL: name: test_anyext_i8toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -405,7 +405,7 @@ body: | --- name: test_anyext_i8toi32 # ALL-LABEL: name: test_anyext_i8toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -440,7 +440,7 @@ body: | --- name: test_anyext_i16toi32 # ALL-LABEL: name: test_anyext_i16toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir index 06f58643008..36a9244fe54 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir @@ -14,7 +14,7 @@ --- name: test_extract_128_idx0 # ALL-LABEL: name: test_extract_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX: registers: @@ -46,7 +46,7 @@ body: | --- name: test_extract_128_idx1 # ALL-LABEL: name: test_extract_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir index 7203b9e6971..f0491b6e0d8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir @@ -23,7 +23,7 @@ --- name: test_extract_128_idx0 # ALL-LABEL: name: test_extract_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -49,7 +49,7 @@ body: | --- name: test_extract_128_idx1 # ALL-LABEL: name: test_extract_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -75,7 +75,7 @@ body: | --- name: test_extract_256_idx0 # ALL-LABEL: name: test_extract_256_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -101,7 +101,7 @@ body: | --- name: test_extract_256_idx1 # ALL-LABEL: name: test_extract_256_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir index 931fd4f7c2c..a34f622db1b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fadd_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fadd_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir index d3ee1b3c4f8..47be0d593e8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir @@ -18,7 +18,7 @@ --- name: test_float # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -63,7 +63,7 @@ body: | --- name: test_double # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir index bd36a8e0626..8741968a5da 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fdiv_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fdiv_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir index 326762d9cf9..826e70dea2d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fmul_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fmul_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir index cd72edd729a..97edc58e69d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir @@ -11,7 +11,7 @@ ... --- name: test -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir index 3b259729ce8..bb6c1e9930d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir @@ -10,7 +10,7 @@ ... --- name: test_fptrunc -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir index 6564f77a261..efc6cd57115 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fsub_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fsub_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir b/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir index ce54b5e405e..0b90620107f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir @@ -9,7 +9,7 @@ ... --- name: test_gep_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir index 685596d5904..9424e1d52b7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir @@ -21,7 +21,7 @@ --- name: test_insert_128_idx0 # ALL-LABEL: name: test_insert_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | --- name: test_insert_128_idx0_undef # ALL-LABEL: name: test_insert_128_idx0_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -83,7 +83,7 @@ body: | --- name: test_insert_128_idx1 # ALL-LABEL: name: test_insert_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -114,7 +114,7 @@ body: | --- name: test_insert_128_idx1_undef # ALL-LABEL: name: test_insert_128_idx1_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir index d3bd3b70920..fefce0bc17c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir @@ -37,7 +37,7 @@ ... --- name: test_insert_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -63,7 +63,7 @@ body: | ... --- name: test_insert_128_idx0_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -88,7 +88,7 @@ body: | ... --- name: test_insert_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -113,7 +113,7 @@ body: | ... --- name: test_insert_128_idx1_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -138,7 +138,7 @@ body: | ... --- name: test_insert_256_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -164,7 +164,7 @@ body: | ... --- name: test_insert_256_idx0_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -189,7 +189,7 @@ body: | ... --- name: test_insert_256_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -214,7 +214,7 @@ body: | ... --- name: test_insert_256_idx1_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir index c20243d0c28..4478ef5a5fc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir @@ -72,7 +72,7 @@ ... --- name: test_lshr_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -108,7 +108,7 @@ body: | ... --- name: test_lshr_i64_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -139,7 +139,7 @@ body: | ... --- name: test_lshr_i64_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -170,7 +170,7 @@ body: | ... --- name: test_lshr_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -206,7 +206,7 @@ body: | ... --- name: test_lshr_i32_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -237,7 +237,7 @@ body: | ... --- name: test_lshr_i32_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -268,7 +268,7 @@ body: | ... --- name: test_lshr_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -307,7 +307,7 @@ body: | ... --- name: test_lshr_i16_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -341,7 +341,7 @@ body: | ... --- name: test_lshr_i16_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -375,7 +375,7 @@ body: | ... --- name: test_lshr_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -414,7 +414,7 @@ body: | ... --- name: test_lshr_i8_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -448,7 +448,7 @@ body: | ... --- name: test_lshr_i8_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir index 70b1a2dfc5c..d9016f907d1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir @@ -101,7 +101,7 @@ ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -139,7 +139,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -177,7 +177,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -215,7 +215,7 @@ body: | ... --- name: test_load_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -253,7 +253,7 @@ body: | ... --- name: test_load_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -303,7 +303,7 @@ body: | ... --- name: test_load_float_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -353,7 +353,7 @@ body: | ... --- name: test_load_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -403,7 +403,7 @@ body: | ... --- name: test_load_double_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -453,7 +453,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -496,7 +496,7 @@ body: | ... --- name: test_store_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -539,7 +539,7 @@ body: | ... --- name: test_store_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -594,7 +594,7 @@ body: | ... --- name: test_store_float_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -649,7 +649,7 @@ body: | ... --- name: test_store_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -705,7 +705,7 @@ body: | ... --- name: test_store_double_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -760,7 +760,7 @@ body: | ... --- name: test_load_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -799,7 +799,7 @@ body: | ... --- name: test_store_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -838,7 +838,7 @@ body: | ... --- name: test_gep_folding -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -891,7 +891,7 @@ body: | ... --- name: test_gep_folding_largeGepIndex -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir index e940a462f07..78be9d573ea 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir @@ -45,7 +45,7 @@ ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -70,7 +70,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -95,7 +95,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -120,7 +120,7 @@ body: | ... --- name: test_store_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -150,7 +150,7 @@ body: | ... --- name: test_store_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -180,7 +180,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -210,7 +210,7 @@ body: | ... --- name: test_load_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -235,7 +235,7 @@ body: | ... --- name: test_store_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir index f366bf33683..a552e5658f1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir @@ -101,7 +101,7 @@ ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -139,7 +139,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -177,7 +177,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -215,7 +215,7 @@ body: | ... --- name: test_load_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -253,7 +253,7 @@ body: | ... --- name: test_load_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -303,7 +303,7 @@ body: | ... --- name: test_load_float_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -353,7 +353,7 @@ body: | ... --- name: test_load_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -403,7 +403,7 @@ body: | ... --- name: test_load_double_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -453,7 +453,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -496,7 +496,7 @@ body: | ... --- name: test_store_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -539,7 +539,7 @@ body: | ... --- name: test_store_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -594,7 +594,7 @@ body: | ... --- name: test_store_float_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -649,7 +649,7 @@ body: | ... --- name: test_store_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -705,7 +705,7 @@ body: | ... --- name: test_store_double_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -760,7 +760,7 @@ body: | ... --- name: test_load_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -799,7 +799,7 @@ body: | ... --- name: test_store_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -838,7 +838,7 @@ body: | ... --- name: test_gep_folding -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -891,7 +891,7 @@ body: | ... --- name: test_gep_folding_largeGepIndex -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir index 84c8d084edc..8b04d5e191c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir @@ -28,7 +28,7 @@ --- # ALL-LABEL: name: test_load_v4i32_noalign name: test_load_v4i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | --- # ALL-LABEL: name: test_load_v4i32_align name: test_load_v4i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -78,7 +78,7 @@ body: | --- # ALL-LABEL: name: test_store_v4i32_align name: test_store_v4i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -106,7 +106,7 @@ body: | --- # ALL-LABEL: name: test_store_v4i32_noalign name: test_store_v4i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir index 4863be2a63e..e1369a60d50 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir @@ -29,7 +29,7 @@ --- name: test_load_v8i32_noalign # ALL-LABEL: name: test_load_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: @@ -69,7 +69,7 @@ body: | --- name: test_load_v8i32_align # ALL-LABEL: name: test_load_v8i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -102,7 +102,7 @@ body: | --- name: test_store_v8i32_noalign # ALL-LABEL: name: test_store_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: @@ -142,7 +142,7 @@ body: | --- name: test_store_v8i32_align # ALL-LABEL: name: test_store_v8i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir index 0de858e55a1..a9175592261 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir @@ -24,7 +24,7 @@ ... --- name: test_load_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -47,7 +47,7 @@ body: | ... --- name: test_load_v16i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -70,7 +70,7 @@ body: | ... --- name: test_store_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -93,7 +93,7 @@ body: | ... --- name: test_store_v16i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir index ab7532f0e0a..8c04cc6f76c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir @@ -9,7 +9,7 @@ --- name: test_merge # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir index d188d3ef9ad..3c003d6cf92 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir @@ -12,7 +12,7 @@ ... --- name: test_merge_v128 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -37,7 +37,7 @@ body: | ... --- name: test_merge_v256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir index d90c4615377..826fb26cb07 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir @@ -20,7 +20,7 @@ ... --- name: test_mul_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -46,7 +46,7 @@ body: | ... --- name: test_mul_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -72,7 +72,7 @@ body: | ... --- name: test_mul_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir b/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir index 3eb963e419b..215926b030b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir @@ -91,7 +91,7 @@ ... --- name: test_mul_v8i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -117,7 +117,7 @@ body: | ... --- name: test_mul_v8i16_avx -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -143,7 +143,7 @@ body: | ... --- name: test_mul_v8i16_avx512bwvl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -169,7 +169,7 @@ body: | ... --- name: test_mul_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -195,7 +195,7 @@ body: | ... --- name: test_mul_v4i32_avx -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -221,7 +221,7 @@ body: | ... --- name: test_mul_v4i32_avx512vl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -247,7 +247,7 @@ body: | ... --- name: test_mul_v2i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -273,7 +273,7 @@ body: | ... --- name: test_mul_v16i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -299,7 +299,7 @@ body: | ... --- name: test_mul_v16i16_avx512bwvl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -325,7 +325,7 @@ body: | ... --- name: test_mul_v8i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -351,7 +351,7 @@ body: | ... --- name: test_mul_v8i32_avx512vl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -377,7 +377,7 @@ body: | ... --- name: test_mul_v4i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -403,7 +403,7 @@ body: | ... --- name: test_mul_v32i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -429,7 +429,7 @@ body: | ... --- name: test_mul_v16i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -455,7 +455,7 @@ body: | ... --- name: test_mul_v8i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir index 832c38dc159..2c13c0afe3e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir @@ -25,7 +25,7 @@ ... --- name: test_or_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_or_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_or_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -115,7 +115,7 @@ body: | ... --- name: test_or_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir index 4323288fe1b..ef70ef5d924 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir @@ -102,7 +102,7 @@ ... --- name: test_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -161,7 +161,7 @@ body: | ... --- name: test_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -220,7 +220,7 @@ body: | ... --- name: test_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -283,7 +283,7 @@ body: | ... --- name: test_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -346,7 +346,7 @@ body: | ... --- name: test_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -411,7 +411,7 @@ body: | ... --- name: test_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir index 1c4dcf4a334..1928093b04d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir @@ -73,7 +73,7 @@ ... --- name: test_shl_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -109,7 +109,7 @@ body: | ... --- name: test_shl_i64_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -140,7 +140,7 @@ body: | ... --- name: test_shl_i64_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -171,7 +171,7 @@ body: | ... --- name: test_shl_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -207,7 +207,7 @@ body: | ... --- name: test_shl_i32_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -238,7 +238,7 @@ body: | ... --- name: test_shl_i32_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -269,7 +269,7 @@ body: | ... --- name: test_shl_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -308,7 +308,7 @@ body: | ... --- name: test_shl_i16_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -342,7 +342,7 @@ body: | ... --- name: test_shl_i16_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -376,7 +376,7 @@ body: | ... --- name: test_shl_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -415,7 +415,7 @@ body: | ... --- name: test_shl_i8_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -449,7 +449,7 @@ body: | ... --- name: test_shl_i8_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir index d9c5ccdf72f..db1cf8183aa 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir @@ -28,7 +28,7 @@ --- name: test_sub_v16i8 # ALL-LABEL: name: test_sub_v16i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -56,7 +56,7 @@ body: | --- name: test_sub_v8i16 # ALL-LABEL: name: test_sub_v8i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -84,7 +84,7 @@ body: | --- name: test_sub_v4i32 # ALL-LABEL: name: test_sub_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -112,7 +112,7 @@ body: | --- name: test_sub_v2i64 # ALL-LABEL: name: test_sub_v2i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir index ae1ae9b1eee..6959dfe6382 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir @@ -26,7 +26,7 @@ --- name: test_sub_v32i8 # ALL-LABEL: name: test_sub_v32i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -52,7 +52,7 @@ body: | --- name: test_sub_v16i16 # ALL-LABEL: name: test_sub_v16i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -78,7 +78,7 @@ body: | --- name: test_sub_v8i32 # ALL-LABEL: name: test_sub_v8i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -104,7 +104,7 @@ body: | --- name: test_sub_v4i64 # ALL-LABEL: name: test_sub_v4i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir index 3e1772a7894..52a948211b2 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir @@ -27,7 +27,7 @@ ... --- name: test_sub_v64i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | ... --- name: test_sub_v32i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -79,7 +79,7 @@ body: | ... --- name: test_sub_v16i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -105,7 +105,7 @@ body: | ... --- name: test_sub_v8i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir index 33aa64463c8..1f46b02082a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir @@ -70,7 +70,7 @@ body: | ... --- name: test_sub_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -100,7 +100,7 @@ body: | ... --- name: test_sub_v4f32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir index 68d2bb119f4..08943172487 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir @@ -34,7 +34,7 @@ ... --- name: trunc_i32toi1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -59,7 +59,7 @@ body: | ... --- name: trunc_i32toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -82,7 +82,7 @@ body: | ... --- name: trunc_i32toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -105,7 +105,7 @@ body: | ... --- name: trunc_i64toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -128,7 +128,7 @@ body: | ... --- name: trunc_i64toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -151,7 +151,7 @@ body: | ... --- name: trunc_i64toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir b/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir index ec9a970a31b..dddebf209bf 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir @@ -17,7 +17,7 @@ ... --- name: test -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -39,7 +39,7 @@ body: | ... --- name: test2 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -69,7 +69,7 @@ body: | ... --- name: test3 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir index bc1f707cafe..39471928d44 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir @@ -10,7 +10,7 @@ --- name: test_unmerge # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir index 2b96ed12dfa..17730f985f9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir @@ -12,7 +12,7 @@ ... --- name: test_unmerge_v128 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -40,7 +40,7 @@ body: | ... --- name: test_unmerge_v256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir index 2e9fb6a7b85..30d214607f0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir @@ -25,7 +25,7 @@ ... --- name: test_xor_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_xor_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_xor_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -115,7 +115,7 @@ body: | ... --- name: test_xor_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir index a131f1f3220..d4f785dfee8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir @@ -11,7 +11,7 @@ --- name: test_global_ptrv # ALL-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir index 83079632b10..67ed879723b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir index 8db6b0f47b0..86879866f10 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir @@ -30,7 +30,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -60,7 +60,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -87,7 +87,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -114,7 +114,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir index f36e73640f1..80382db9427 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir @@ -24,7 +24,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -56,7 +56,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -88,7 +88,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir index 13174eab502..466990bf7f8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir @@ -25,7 +25,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -87,7 +87,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -149,7 +149,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir index d4b78de113d..85c9b6d9e86 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir @@ -24,7 +24,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -83,7 +83,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -142,7 +142,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir index b2213ab5b73..77ff45293fb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir @@ -25,7 +25,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -87,7 +87,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -149,7 +149,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir index 2fcdb200730..6b740a18c14 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir index 90e71db9e8b..38ce2160b58 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir @@ -30,7 +30,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -60,7 +60,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -88,7 +88,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -116,7 +116,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir index 99781b603aa..25904de22ba 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir @@ -24,7 +24,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -60,7 +60,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -97,7 +97,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir index 164d53ea79d..93bab680ee9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir @@ -25,7 +25,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -87,7 +87,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -150,7 +150,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir index bd181fb5f00..ea548c296dc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir @@ -15,7 +15,7 @@ ... --- name: trap -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir index 7eff94478b2..b36c17fe8b3 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir @@ -25,7 +25,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -87,7 +87,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -151,7 +151,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir index 10d07daca88..fe97a2bcb39 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir @@ -25,7 +25,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -87,7 +87,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -151,7 +151,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir index 01c9f49e106..95cc0d90c75 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir @@ -11,7 +11,7 @@ --- name: test_global_ptrv # ALL-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir index c4083184b41..4eabd9a4c1e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir @@ -146,7 +146,7 @@ ... --- name: fcmp_float_oeq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -181,7 +181,7 @@ body: | ... --- name: fcmp_float_ogt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -216,7 +216,7 @@ body: | ... --- name: fcmp_float_oge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -251,7 +251,7 @@ body: | ... --- name: fcmp_float_olt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -286,7 +286,7 @@ body: | ... --- name: fcmp_float_ole -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -321,7 +321,7 @@ body: | ... --- name: fcmp_float_one -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -356,7 +356,7 @@ body: | ... --- name: fcmp_float_ord -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -391,7 +391,7 @@ body: | ... --- name: fcmp_float_uno -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -426,7 +426,7 @@ body: | ... --- name: fcmp_float_ueq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -461,7 +461,7 @@ body: | ... --- name: fcmp_float_ugt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -496,7 +496,7 @@ body: | ... --- name: fcmp_float_uge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -531,7 +531,7 @@ body: | ... --- name: fcmp_float_ult -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -566,7 +566,7 @@ body: | ... --- name: fcmp_float_ule -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -601,7 +601,7 @@ body: | ... --- name: fcmp_float_une -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -636,7 +636,7 @@ body: | ... --- name: fcmp_double_oeq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -671,7 +671,7 @@ body: | ... --- name: fcmp_double_ogt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -706,7 +706,7 @@ body: | ... --- name: fcmp_double_oge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -741,7 +741,7 @@ body: | ... --- name: fcmp_double_olt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -776,7 +776,7 @@ body: | ... --- name: fcmp_double_ole -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -811,7 +811,7 @@ body: | ... --- name: fcmp_double_one -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -846,7 +846,7 @@ body: | ... --- name: fcmp_double_ord -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -881,7 +881,7 @@ body: | ... --- name: fcmp_double_uno -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -916,7 +916,7 @@ body: | ... --- name: fcmp_double_ueq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -951,7 +951,7 @@ body: | ... --- name: fcmp_double_ugt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -986,7 +986,7 @@ body: | ... --- name: fcmp_double_uge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1021,7 +1021,7 @@ body: | ... --- name: fcmp_double_ult -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1056,7 +1056,7 @@ body: | ... --- name: fcmp_double_ule -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1091,7 +1091,7 @@ body: | ... --- name: fcmp_double_une -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir index 194b2a77666..5d244d4a9c0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir @@ -54,7 +54,7 @@ ... --- name: float_to_int8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -81,7 +81,7 @@ body: | ... --- name: float_to_int16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -108,7 +108,7 @@ body: | ... --- name: float_to_int32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -134,7 +134,7 @@ body: | ... --- name: float_to_int64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -160,7 +160,7 @@ body: | ... --- name: double_to_int8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -187,7 +187,7 @@ body: | ... --- name: double_to_int16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -214,7 +214,7 @@ body: | ... --- name: double_to_int32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -240,7 +240,7 @@ body: | ... --- name: double_to_int64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir index 361e39b6e8f..90aed846b95 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir index 6e46ae2a785..3dc342e6ee0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir @@ -36,7 +36,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -62,7 +62,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -85,7 +85,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -108,7 +108,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -131,7 +131,7 @@ body: | ... --- name: ptrtoint_s64_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir index 5314c91fe03..faccc3750c8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir @@ -29,7 +29,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -61,7 +61,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -93,7 +93,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -119,7 +119,7 @@ body: | ... --- name: test_sdiv_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir index 7a69731652d..5713ddf22d4 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir @@ -74,7 +74,7 @@ ... --- name: int8_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -108,7 +108,7 @@ body: | ... --- name: int16_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -142,7 +142,7 @@ body: | ... --- name: int32_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -168,7 +168,7 @@ body: | ... --- name: int64_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -194,7 +194,7 @@ body: | ... --- name: int8_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -228,7 +228,7 @@ body: | ... --- name: int16_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -262,7 +262,7 @@ body: | ... --- name: int32_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -288,7 +288,7 @@ body: | ... --- name: int64_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir index 67787cc854b..f02442f2b85 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir @@ -29,7 +29,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -88,7 +88,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -147,7 +147,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -200,7 +200,7 @@ body: | ... --- name: test_srem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir index 027c1112801..35073e2bcb1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir @@ -29,7 +29,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -88,7 +88,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -147,7 +147,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -200,7 +200,7 @@ body: | ... --- name: test_udiv_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir index 35e5366b1d9..c0ca5ae74fc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir @@ -29,7 +29,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -88,7 +88,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -147,7 +147,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -200,7 +200,7 @@ body: | ... --- name: test_urem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir index 834f214ad07..0795539e7c1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir @@ -56,7 +56,7 @@ ... --- name: zext_i1_to_i8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -83,7 +83,7 @@ body: | ... --- name: zext_i1_to_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -110,7 +110,7 @@ body: | ... --- name: zext_i1_to_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -137,7 +137,7 @@ body: | ... --- name: zext_i1_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -164,7 +164,7 @@ body: | ... --- name: zext_i8_to_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -191,7 +191,7 @@ body: | ... --- name: zext_i8_to_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -218,7 +218,7 @@ body: | ... --- name: zext_i8_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -245,7 +245,7 @@ body: | ... --- name: zext_i16_to_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -272,7 +272,7 @@ body: | ... --- name: zext_i16_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -299,7 +299,7 @@ body: | ... --- name: zext_i32_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir index 9c0396db899..e60720cfa87 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir @@ -146,7 +146,7 @@ ... --- name: fcmp_float_oeq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -186,7 +186,7 @@ body: | ... --- name: fcmp_float_ogt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -224,7 +224,7 @@ body: | ... --- name: fcmp_float_oge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -262,7 +262,7 @@ body: | ... --- name: fcmp_float_olt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -300,7 +300,7 @@ body: | ... --- name: fcmp_float_ole -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -338,7 +338,7 @@ body: | ... --- name: fcmp_float_one -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -376,7 +376,7 @@ body: | ... --- name: fcmp_float_ord -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -414,7 +414,7 @@ body: | ... --- name: fcmp_float_uno -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -452,7 +452,7 @@ body: | ... --- name: fcmp_float_ueq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -490,7 +490,7 @@ body: | ... --- name: fcmp_float_ugt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -528,7 +528,7 @@ body: | ... --- name: fcmp_float_uge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -566,7 +566,7 @@ body: | ... --- name: fcmp_float_ult -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -604,7 +604,7 @@ body: | ... --- name: fcmp_float_ule -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -642,7 +642,7 @@ body: | ... --- name: fcmp_float_une -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -682,7 +682,7 @@ body: | ... --- name: fcmp_double_oeq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -722,7 +722,7 @@ body: | ... --- name: fcmp_double_ogt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -760,7 +760,7 @@ body: | ... --- name: fcmp_double_oge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -798,7 +798,7 @@ body: | ... --- name: fcmp_double_olt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -836,7 +836,7 @@ body: | ... --- name: fcmp_double_ole -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -874,7 +874,7 @@ body: | ... --- name: fcmp_double_one -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -912,7 +912,7 @@ body: | ... --- name: fcmp_double_ord -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -950,7 +950,7 @@ body: | ... --- name: fcmp_double_uno -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -988,7 +988,7 @@ body: | ... --- name: fcmp_double_ueq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1026,7 +1026,7 @@ body: | ... --- name: fcmp_double_ugt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1064,7 +1064,7 @@ body: | ... --- name: fcmp_double_uge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1102,7 +1102,7 @@ body: | ... --- name: fcmp_double_ult -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1140,7 +1140,7 @@ body: | ... --- name: fcmp_double_ule -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1178,7 +1178,7 @@ body: | ... --- name: fcmp_double_une -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir index b5085d59be8..6ff271d487e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir @@ -54,7 +54,7 @@ ... --- name: float_to_int8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -85,7 +85,7 @@ body: | ... --- name: float_to_int16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -116,7 +116,7 @@ body: | ... --- name: float_to_int32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -144,7 +144,7 @@ body: | ... --- name: float_to_int64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -172,7 +172,7 @@ body: | ... --- name: double_to_int8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -203,7 +203,7 @@ body: | ... --- name: double_to_int16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -234,7 +234,7 @@ body: | ... --- name: double_to_int32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -262,7 +262,7 @@ body: | ... --- name: double_to_int64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir index 33766abe4c4..f9ce11e48f7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir index 94027c41212..4f330f6119f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir @@ -36,7 +36,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -63,7 +63,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -88,7 +88,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -113,7 +113,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -138,7 +138,7 @@ body: | ... --- name: ptrtoint_s64_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir index 68f21c8ea7d..d3a1608be52 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir @@ -29,7 +29,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -65,7 +65,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -102,7 +102,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -133,7 +133,7 @@ body: | ... --- name: test_sdiv_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir index eeb976cae38..f853fe7bbb3 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir @@ -46,7 +46,7 @@ ... --- name: int32_to_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -74,7 +74,7 @@ body: | ... --- name: int64_to_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -102,7 +102,7 @@ body: | ... --- name: int32_to_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -130,7 +130,7 @@ body: | ... --- name: int64_to_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir index 53c444e327e..a0551f1f59d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir @@ -29,7 +29,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -90,7 +90,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -152,7 +152,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -208,7 +208,7 @@ body: | ... --- name: test_srem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir index 44b057cbf32..71c03fd6e28 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir @@ -29,7 +29,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -90,7 +90,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -153,7 +153,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -210,7 +210,7 @@ body: | ... --- name: test_udiv_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir index 3fa33e6f34a..c25db2b6f0f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir @@ -29,7 +29,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -90,7 +90,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -153,7 +153,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -210,7 +210,7 @@ body: | ... --- name: test_urem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir index b0b445de800..c1a339422c8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir @@ -56,7 +56,7 @@ ... --- name: zext_i1_to_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -87,7 +87,7 @@ body: | ... --- name: zext_i1_to_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -118,7 +118,7 @@ body: | ... --- name: zext_i1_to_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -148,7 +148,7 @@ body: | ... --- name: zext_i1_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -180,7 +180,7 @@ body: | ... --- name: zext_i8_to_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -211,7 +211,7 @@ body: | ... --- name: zext_i8_to_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -242,7 +242,7 @@ body: | ... --- name: zext_i8_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -274,7 +274,7 @@ body: | ... --- name: zext_i16_to_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -305,7 +305,7 @@ body: | ... --- name: zext_i16_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -337,7 +337,7 @@ body: | ... --- name: zext_i32_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/PR37310.mir b/llvm/test/CodeGen/X86/PR37310.mir index c35462bb8ae..05e3f2c561f 100644 --- a/llvm/test/CodeGen/X86/PR37310.mir +++ b/llvm/test/CodeGen/X86/PR37310.mir @@ -64,7 +64,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/adx-commute.mir b/llvm/test/CodeGen/X86/adx-commute.mir index 1e204e33913..e2023c12293 100644 --- a/llvm/test/CodeGen/X86/adx-commute.mir +++ b/llvm/test/CodeGen/X86/adx-commute.mir @@ -54,7 +54,7 @@ ... --- name: adcx32_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -99,7 +99,7 @@ body: | ... --- name: adcx64_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -144,7 +144,7 @@ body: | ... --- name: adox32_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -189,7 +189,7 @@ body: | ... --- name: adox64_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir index 82cb9a786c2..c90c2f05b4f 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir @@ -95,7 +95,7 @@ ... --- name: debug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -153,7 +153,7 @@ body: | ... --- name: nodebug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir index c14d0f6c25b..17b6b8744be 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir @@ -106,7 +106,7 @@ ... --- name: debug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir index 3ae44db4f75..3290ab9017a 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir @@ -122,7 +122,7 @@ ... --- name: debug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir b/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir index cfddb1f0b8b..9ae885c94c6 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir @@ -28,7 +28,7 @@ ... --- name: test_imm_store -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/avoid-sfb-offset.mir b/llvm/test/CodeGen/X86/avoid-sfb-offset.mir index 659f1a0923e..027cc399f0f 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-offset.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-offset.mir @@ -35,7 +35,7 @@ ... --- name: test_offset -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avx512f-256-set0.mir b/llvm/test/CodeGen/X86/avx512f-256-set0.mir index 45fbafae11d..de240a6f376 100644 --- a/llvm/test/CodeGen/X86/avx512f-256-set0.mir +++ b/llvm/test/CodeGen/X86/avx512f-256-set0.mir @@ -25,7 +25,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/bad-tls-fold.mir b/llvm/test/CodeGen/X86/bad-tls-fold.mir index 550d0db3cb0..597a83d8938 100644 --- a/llvm/test/CodeGen/X86/bad-tls-fold.mir +++ b/llvm/test/CodeGen/X86/bad-tls-fold.mir @@ -18,7 +18,7 @@ --- # CHECK-LABEL: or: name: or -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } @@ -48,7 +48,7 @@ body: | --- # CHECK-LABEL: and: name: and -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/block-placement.mir b/llvm/test/CodeGen/X86/block-placement.mir index 04444bea952..1d661687d25 100644 --- a/llvm/test/CodeGen/X86/block-placement.mir +++ b/llvm/test/CodeGen/X86/block-placement.mir @@ -40,7 +40,7 @@ --- # CHECK: name: f name: f -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } diff --git a/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir b/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir index d311bb2458d..aa6d317acc3 100644 --- a/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir +++ b/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir @@ -70,7 +70,7 @@ ... --- name: f -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir b/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir index f218c0c6477..e0412817a04 100644 --- a/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir +++ b/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir @@ -83,7 +83,7 @@ # CHECK: bb.12.for.body.10 name: _Z3fn1v -alignment: 4 +alignment: 16 tracksRegLiveness: true constants: body: | diff --git a/llvm/test/CodeGen/X86/domain-reassignment.mir b/llvm/test/CodeGen/X86/domain-reassignment.mir index 9fa779d7653..38755344849 100644 --- a/llvm/test/CodeGen/X86/domain-reassignment.mir +++ b/llvm/test/CodeGen/X86/domain-reassignment.mir @@ -49,7 +49,7 @@ ... --- name: test_fcmp_storefloat -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -202,7 +202,7 @@ body: | ... --- name: test_8bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -323,7 +323,7 @@ body: | ... --- name: test_16bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -441,7 +441,7 @@ body: | ... --- name: test_32bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -544,7 +544,7 @@ body: | ... --- name: test_64bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -647,7 +647,7 @@ body: | ... --- name: test_16bitext -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -716,7 +716,7 @@ body: | ... --- name: test_32bitext -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -789,7 +789,7 @@ body: | ... --- name: test_64bitext -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/fixup-bw-inst.mir b/llvm/test/CodeGen/X86/fixup-bw-inst.mir index fe39251d6e9..0f0b4545791 100644 --- a/llvm/test/CodeGen/X86/fixup-bw-inst.mir +++ b/llvm/test/CodeGen/X86/fixup-bw-inst.mir @@ -39,7 +39,7 @@ --- # CHECK-LABEL: name: test1 name: test1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rax' } @@ -61,7 +61,7 @@ body: | --- # CHECK-LABEL: name: test2 name: test2 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rax' } @@ -82,7 +82,7 @@ body: | --- # CHECK-LABEL: name: test3 name: test3 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -116,7 +116,7 @@ body: | --- # CHECK-LABEL: name: test4 name: test4 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r9d' } @@ -136,7 +136,7 @@ body: | --- # CHECK-LABEL: name: test5 name: test5 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$ch', reg: '$bl' } diff --git a/llvm/test/CodeGen/X86/implicit-null-checks.mir b/llvm/test/CodeGen/X86/implicit-null-checks.mir index d7983553cc9..e6147f56ed7 100644 --- a/llvm/test/CodeGen/X86/implicit-null-checks.mir +++ b/llvm/test/CodeGen/X86/implicit-null-checks.mir @@ -384,7 +384,7 @@ --- name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -424,7 +424,7 @@ body: | ... --- name: imp_null_check_with_bitwise_op_1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -468,7 +468,7 @@ body: | --- name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -509,7 +509,7 @@ body: | --- name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -549,7 +549,7 @@ body: | --- name: imp_null_check_with_bitwise_op_4 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_4 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -590,7 +590,7 @@ body: | --- name: no_hoist_across_call # CHECK-LABEL: name: no_hoist_across_call -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -638,7 +638,7 @@ name: dependency_live_in_hazard # an implicit null check -- hoisting it will require hosting the move # to $esi and we cannot do that without clobbering the use of $rsi in # the first instruction in bb.1.not_null. -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -672,7 +672,7 @@ name: use_alternate_load_op # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -703,7 +703,7 @@ name: imp_null_check_gep_load_with_use_dep # CHECK: bb.0.entry: # CHECK: $eax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from %ir.x) # CHECK-NEXT: JMP_1 %bb.1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -735,7 +735,7 @@ name: imp_null_check_load_with_base_sep # CHECK: $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags # CHECK-NEXT: $esi = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags # CHECK-NEXT: JMP_1 %bb.1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -768,7 +768,7 @@ name: inc_store # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -798,7 +798,7 @@ name: inc_store_plus_offset # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -829,7 +829,7 @@ name: inc_store_with_dep # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -860,7 +860,7 @@ name: inc_store_with_dep_in_null # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -895,7 +895,7 @@ name: inc_store_with_volatile # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -925,7 +925,7 @@ name: inc_store_with_two_dep # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -957,7 +957,7 @@ name: inc_store_with_redefined_base # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -988,7 +988,7 @@ name: inc_store_with_reused_base # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1020,7 +1020,7 @@ name: inc_store_across_call # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1062,7 +1062,7 @@ name: inc_store_with_dep_in_dep # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1095,7 +1095,7 @@ name: inc_store_with_load_over_store # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1127,7 +1127,7 @@ name: inc_store_with_store_over_load # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1159,7 +1159,7 @@ name: inc_store_with_store_over_store # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1190,7 +1190,7 @@ name: inc_store_with_load_and_store # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1221,7 +1221,7 @@ name: inc_store_and_load_no_alias # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1253,7 +1253,7 @@ name: inc_store_and_load_alias # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1285,7 +1285,7 @@ name: inc_spill_dep # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true stack: - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8} diff --git a/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir b/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir index 97f0064c475..6e83b207c2c 100644 --- a/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir +++ b/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir @@ -22,7 +22,7 @@ # that clobber the register used in TEST. name: reg-rewrite -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } diff --git a/llvm/test/CodeGen/X86/late-remat-update.mir b/llvm/test/CodeGen/X86/late-remat-update.mir index 31b6e7e71bc..a8fdc2ae5ac 100644 --- a/llvm/test/CodeGen/X86/late-remat-update.mir +++ b/llvm/test/CodeGen/X86/late-remat-update.mir @@ -54,7 +54,7 @@ ... --- name: _Z3fooi -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/lea-opt-with-debug.mir b/llvm/test/CodeGen/X86/lea-opt-with-debug.mir index a1cf2041db6..c2fcb7c9d6a 100644 --- a/llvm/test/CodeGen/X86/lea-opt-with-debug.mir +++ b/llvm/test/CodeGen/X86/lea-opt-with-debug.mir @@ -63,7 +63,7 @@ ... --- name: fn1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/leaFixup32.mir b/llvm/test/CodeGen/X86/leaFixup32.mir index 6d57cf2d977..f614a4ad975 100644 --- a/llvm/test/CodeGen/X86/leaFixup32.mir +++ b/llvm/test/CodeGen/X86/leaFixup32.mir @@ -78,7 +78,7 @@ ... --- name: test2add_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -113,7 +113,7 @@ body: | ... --- name: test2add_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -148,7 +148,7 @@ body: | ... --- name: test1add_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -182,7 +182,7 @@ body: | ... --- name: testleaadd_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -218,7 +218,7 @@ body: | ... --- name: testleaadd_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -254,7 +254,7 @@ body: | ... --- name: test1lea_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -289,7 +289,7 @@ body: | ... --- name: test2addi32_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -324,7 +324,7 @@ body: | ... --- name: test1mov1add_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -360,7 +360,7 @@ body: | ... --- name: testleaadd_ebp_index_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -395,7 +395,7 @@ body: | ... --- name: testleaadd_ebp_index2_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -430,7 +430,7 @@ body: | ... --- name: test_skip_opt_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -464,7 +464,7 @@ body: | ... --- name: test_skip_eflags_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/leaFixup64.mir b/llvm/test/CodeGen/X86/leaFixup64.mir index fa738adfd06..317c219992c 100644 --- a/llvm/test/CodeGen/X86/leaFixup64.mir +++ b/llvm/test/CodeGen/X86/leaFixup64.mir @@ -151,7 +151,7 @@ ... --- name: testleaadd_64_32_1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -186,7 +186,7 @@ body: | ... --- name: testleaadd_rbp_64_32_1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -221,7 +221,7 @@ body: | ... --- name: test1lea_rbp_64_32_1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -255,7 +255,7 @@ body: | ... --- name: test2add_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -290,7 +290,7 @@ body: | ... --- name: test2add_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -325,7 +325,7 @@ body: | ... --- name: test1add_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -359,7 +359,7 @@ body: | ... --- name: testleaadd_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -395,7 +395,7 @@ body: | ... --- name: testleaadd_rbp_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -431,7 +431,7 @@ body: | ... --- name: test1lea_rbp_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -466,7 +466,7 @@ body: | ... --- name: testleaadd_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -502,7 +502,7 @@ body: | ... --- name: testleaadd_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -538,7 +538,7 @@ body: | ... --- name: test1lea_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -573,7 +573,7 @@ body: | ... --- name: test8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -609,7 +609,7 @@ body: | ... --- name: testleaaddi32_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -644,7 +644,7 @@ body: | ... --- name: test1mov1add_rbp_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -678,7 +678,7 @@ body: | ... --- name: testleaadd_rbp_index_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -712,7 +712,7 @@ body: | ... --- name: testleaadd_rbp_index2_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -746,7 +746,7 @@ body: | ... --- name: test2addi32_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -781,7 +781,7 @@ body: | ... --- name: test1mov1add_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -816,7 +816,7 @@ body: | ... --- name: testleaadd_rbp_index_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -851,7 +851,7 @@ body: | ... --- name: testleaadd_rbp_index2_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -886,7 +886,7 @@ body: | ... --- name: test_skip_opt_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -920,7 +920,7 @@ body: | ... --- name: test_skip_eflags_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -962,7 +962,7 @@ body: | ... --- name: test_skip_opt_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -996,7 +996,7 @@ body: | ... --- name: test_skip_eflags_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/limit-split-cost.mir b/llvm/test/CodeGen/X86/limit-split-cost.mir index 59c76661d0b..ac686826b4a 100644 --- a/llvm/test/CodeGen/X86/limit-split-cost.mir +++ b/llvm/test/CodeGen/X86/limit-split-cost.mir @@ -71,7 +71,7 @@ ... --- name: _Z3fooi -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/movtopush.mir b/llvm/test/CodeGen/X86/movtopush.mir index 98769a213bb..3d286bb498d 100644 --- a/llvm/test/CodeGen/X86/movtopush.mir +++ b/llvm/test/CodeGen/X86/movtopush.mir @@ -54,7 +54,7 @@ # CHECK-NEXT: ADJCALLSTACKUP32 20, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp # CHECK-NEXT: RET 0 name: test9 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/non-value-mem-operand.mir b/llvm/test/CodeGen/X86/non-value-mem-operand.mir index 8e27cde9c11..8682d0657b2 100644 --- a/llvm/test/CodeGen/X86/non-value-mem-operand.mir +++ b/llvm/test/CodeGen/X86/non-value-mem-operand.mir @@ -120,7 +120,7 @@ ...
---
name: eggs
-alignment: 4
+alignment: 16
tracksRegLiveness: true
fixedStack:
- { id: 0, type: spill-slot, offset: -56, size: 8, alignment: 8, callee-saved-register: '$rbx' }
diff --git a/llvm/test/CodeGen/X86/opt_phis2.mir b/llvm/test/CodeGen/X86/opt_phis2.mir index 738a2da1f36..3683d31db17 100644 --- a/llvm/test/CodeGen/X86/opt_phis2.mir +++ b/llvm/test/CodeGen/X86/opt_phis2.mir @@ -9,7 +9,7 @@ ... --- name: test -alignment: 4 +alignment: 16 tracksRegLiveness: true jumpTable: kind: block-address diff --git a/llvm/test/CodeGen/X86/peephole-fold-testrr.mir b/llvm/test/CodeGen/X86/peephole-fold-testrr.mir index 1594f52cb0c..08e7c8bda04 100644 --- a/llvm/test/CodeGen/X86/peephole-fold-testrr.mir +++ b/llvm/test/CodeGen/X86/peephole-fold-testrr.mir @@ -22,7 +22,7 @@ ... --- name: atomic -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } @@ -55,7 +55,7 @@ body: | ... --- name: nonatomic_unoptimized -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir b/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir index 6487f4851aa..c0e5b508958 100644 --- a/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir +++ b/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir @@ -65,7 +65,7 @@ # CHECK-NEXT: DBG_VALUE $eax, # CHECK: bb.2: name: x1 -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/X86/pr30821.mir b/llvm/test/CodeGen/X86/pr30821.mir index d134175652c..7ac7e3668e0 100644 --- a/llvm/test/CodeGen/X86/pr30821.mir +++ b/llvm/test/CodeGen/X86/pr30821.mir @@ -16,7 +16,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/pr38952.mir b/llvm/test/CodeGen/X86/pr38952.mir index 9a43dd2d8ce..ba2ffa8fefc 100644 --- a/llvm/test/CodeGen/X86/pr38952.mir +++ b/llvm/test/CodeGen/X86/pr38952.mir @@ -31,7 +31,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/pre-coalesce.mir b/llvm/test/CodeGen/X86/pre-coalesce.mir index 8a783a79609..3051c009eb9 100644 --- a/llvm/test/CodeGen/X86/pre-coalesce.mir +++ b/llvm/test/CodeGen/X86/pre-coalesce.mir @@ -46,7 +46,7 @@ # CHECK: JCC_1 %[[L1]], 5 name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/regalloc-copy-hints.mir b/llvm/test/CodeGen/X86/regalloc-copy-hints.mir index 64a6a738084..591ba640206 100644 --- a/llvm/test/CodeGen/X86/regalloc-copy-hints.mir +++ b/llvm/test/CodeGen/X86/regalloc-copy-hints.mir @@ -15,7 +15,7 @@ # CHECK: hints: $ebx $edi # CHECK-NOT: hints: $ebx $edi $ebx $edi name: fun -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir b/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir index 33827e733b1..8bb10127f3c 100644 --- a/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir +++ b/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir @@ -94,7 +94,7 @@ ... --- name: '@shrink_wrap_basic@16' -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir b/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir index 697e03d5c33..9536ba1dbc2 100644 --- a/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir +++ b/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir @@ -11,7 +11,7 @@ --- name: bar # CHECK-LABEL: name: bar -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/X86/stack-folding-adx.mir b/llvm/test/CodeGen/X86/stack-folding-adx.mir index ec74eeb3a34..99e24cb12d1 100644 --- a/llvm/test/CodeGen/X86/stack-folding-adx.mir +++ b/llvm/test/CodeGen/X86/stack-folding-adx.mir @@ -61,7 +61,7 @@ ... --- name: stack_fold_adcx32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -113,7 +113,7 @@ body: | ... --- name: stack_fold_adcx64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -165,7 +165,7 @@ body: | ... --- name: stack_fold_adox32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -217,7 +217,7 @@ body: | ... --- name: stack_fold_adox64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/stack-folding-bmi2.mir b/llvm/test/CodeGen/X86/stack-folding-bmi2.mir index ab97872e443..604f7bdacdf 100644 --- a/llvm/test/CodeGen/X86/stack-folding-bmi2.mir +++ b/llvm/test/CodeGen/X86/stack-folding-bmi2.mir @@ -33,7 +33,7 @@ ... --- name: stack_fold_mulx_u32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -68,7 +68,7 @@ body: | ... --- name: stack_fold_mulx_u64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir b/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir index b7755ba5d52..d95bfc0810d 100644 --- a/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir +++ b/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir @@ -4,7 +4,7 @@ name: main4k # CHECK-LABEL: name: main4k -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: maxAlignment: 8 diff --git a/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir b/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir index 77872fb46f4..d1e7ff2102a 100644 --- a/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir +++ b/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir @@ -347,7 +347,7 @@ ... --- name: "\x01+[MyObject doWithSize:]" -alignment: 2 +alignment: 4 tracksRegLiveness: true liveins: - { reg: '$x0' } @@ -653,7 +653,7 @@ body: | ... --- name: asan.module_ctor -alignment: 2 +alignment: 4 tracksRegLiveness: true frameInfo: stackSize: 16 diff --git a/llvm/test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir b/llvm/test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir index 24dbb26b4ca..90dd2c4bbec 100644 --- a/llvm/test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir +++ b/llvm/test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir @@ -54,7 +54,7 @@ --- # CHECK-LABEL: name: f1 name: f1 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true selected: true diff --git a/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir b/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir index 0b92d6b3a5f..622a52fc8e9 100644 --- a/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir +++ b/llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir @@ -138,7 +138,7 @@ ... --- name: _ZN1BC2Ev -alignment: 1 +alignment: 2 liveins: - { reg: '$r0' } frameInfo: @@ -174,7 +174,7 @@ body: | ... --- name: _ZN1BC1Ev -alignment: 1 +alignment: 2 liveins: - { reg: '$r0' } frameInfo: diff --git a/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir b/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir index 13c5935d0cf..2e29ea53967 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir @@ -105,7 +105,7 @@ ... --- name: f -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir b/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir index d2a8d4cd322..fbf9b345468 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir @@ -146,7 +146,7 @@ ... --- name: _ZN1v2bvEv -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir index cf4b6c43a72..56b6b4d2a25 100644 --- a/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir +++ b/llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir @@ -68,7 +68,7 @@ ... --- name: foo -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir b/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir index 868321bab2a..9bb255a6525 100644 --- a/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir +++ b/llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir @@ -68,7 +68,7 @@ ... --- name: f -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir b/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir index 69b4f7a07a4..c741c402238 100644 --- a/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir +++ b/llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir @@ -68,7 +68,7 @@ ... --- name: f -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir b/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir index 39b8b4341fa..b7d51a13b7e 100644 --- a/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir +++ b/llvm/test/DebugInfo/MIR/ARM/split-superreg.mir @@ -68,7 +68,7 @@ ... --- name: f -alignment: 1 +alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir index a45f6031c21..1187dd43314 100644 --- a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir +++ b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir @@ -110,7 +110,7 @@ ... --- name: foo -alignment: 2 +alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir index 7b29eb44267..52df7ae9751 100644 --- a/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir +++ b/llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir @@ -91,7 +91,7 @@ ... --- name: foo -alignment: 3 +alignment: 8 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir b/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir index 2cb3bd446ee..748c896e0bf 100644 --- a/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir +++ b/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir @@ -60,7 +60,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$edi' } diff --git a/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir b/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir index 06ed00cf31e..075d356c6bd 100644 --- a/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir +++ b/llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir @@ -52,7 +52,7 @@ ... --- name: fn1 -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0.entry: diff --git a/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir b/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir index e8100b71eff..95306835062 100644 --- a/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir +++ b/llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir @@ -55,7 +55,7 @@ ... --- name: f -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir b/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir index f78abfc2d57..2ba38666d0c 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir @@ -126,7 +126,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 frameInfo: stackSize: 24 offsetAdjustment: -24 diff --git a/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir b/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir index d273531adf4..445a2065941 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir @@ -65,7 +65,7 @@ ... --- name: fn1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: [] body: | diff --git a/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir b/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir index c585293381f..c6630047c7e 100644 --- a/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir +++ b/llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir @@ -57,7 +57,7 @@ ... --- name: '$S4main1fyyF' -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/empty-inline.mir b/llvm/test/DebugInfo/MIR/X86/empty-inline.mir index 837042f045e..09bfafe1746 100644 --- a/llvm/test/DebugInfo/MIR/X86/empty-inline.mir +++ b/llvm/test/DebugInfo/MIR/X86/empty-inline.mir @@ -71,7 +71,7 @@ ... --- name: _ZN1C5m_fn3Ev -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir b/llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir index 0c7edf312d9..4e259f9b0c3 100644 --- a/llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir +++ b/llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir @@ -200,7 +200,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir index 0c61c25439b..c55269951aa 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -159,7 +159,7 @@ ... --- name: add -alignment: 4 +alignment: 16 exposesReturnsTwice: false tracksRegLiveness: true liveins: diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir index 70c3fb59866..ba748b989c4 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir @@ -99,7 +99,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore-collide.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore-collide.mir index 3d133d598c0..52020dcce81 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore-collide.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore-collide.mir @@ -39,7 +39,7 @@ ... --- name: baaar -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir index 171a48f158e..aedb31371bd 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir @@ -184,7 +184,7 @@ ... --- name: f -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -306,7 +306,7 @@ body: | # CHECK-NEXT: DBG_VALUE $rbx, $noreg, ![[QVAR]], !DIExpression(DW_OP_LLVM_fragment, 32, 32) name: g -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi', virtual-reg: '' } @@ -386,7 +386,7 @@ body: | # CHECK: DBG_VALUE $rdi, $noreg, ![[RVAR]], !DIExpression(DW_OP_plus_uconst, 1) name: h -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi', virtual-reg: '' } @@ -499,7 +499,7 @@ body: | # CHECK: DBG_VALUE $rsp, 0, ![[SVAR]], !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_plus_uconst, 1) # CHECK: DBG_VALUE $rdi, $noreg, ![[SVAR]], !DIExpression(DW_OP_plus_uconst, 1) name: i -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi', virtual-reg: '' } diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir index e385c7d6521..38a76ed8134 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir @@ -302,7 +302,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir index 2b132fd3df9..2cf52611baf 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir @@ -159,7 +159,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false tracksRegLiveness: true liveins: diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir index 4a2f96c5d5e..60d530f423f 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir @@ -95,7 +95,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir index ac0d519ddfe..837d9c21b48 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir @@ -93,7 +93,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir index dd8310f35cd..1db981ba1d2 100644 --- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir +++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir @@ -122,7 +122,7 @@ ... --- name: f -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -166,7 +166,7 @@ body: | ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir index c11714a275f..6da868ea039 100644 --- a/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir +++ b/llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir @@ -85,7 +85,7 @@ ... --- name: bar -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist.mir b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist.mir index 0797e89d2c6..eb5c85efc5e 100644 --- a/llvm/test/DebugInfo/MIR/X86/mlicm-hoist.mir +++ b/llvm/test/DebugInfo/MIR/X86/mlicm-hoist.mir @@ -89,7 +89,7 @@ ... --- name: Process -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir index 3967360f4f8..c885460239a 100644 --- a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir +++ b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir @@ -62,7 +62,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$edi' } diff --git a/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir b/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir index 742f4657edf..2c38dedad54 100644 --- a/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir +++ b/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir @@ -42,7 +42,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir b/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir index f86dd6b4ede..746bcb9c71b 100644 --- a/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir +++ b/llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir @@ -100,7 +100,7 @@ ... --- name: main -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: maxAlignment: 4 diff --git a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir index 8601893cdc7..613aea7b295 100644 --- a/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir +++ b/llvm/test/DebugInfo/MIR/X86/regcoalescer.mir @@ -34,7 +34,7 @@ ... --- name: main -alignment: 4 +alignment: 16 registers: - { id: 0, class: gr32, preferred-register: '' } body: | diff --git a/llvm/test/DebugInfo/X86/debug-loc-asan.mir b/llvm/test/DebugInfo/X86/debug-loc-asan.mir index 1b92e0cedde..22624736118 100644 --- a/llvm/test/DebugInfo/X86/debug-loc-asan.mir +++ b/llvm/test/DebugInfo/X86/debug-loc-asan.mir @@ -185,7 +185,7 @@ ... --- name: _Z3bari -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$edi' } diff --git a/llvm/test/DebugInfo/X86/debug-loc-offset.mir b/llvm/test/DebugInfo/X86/debug-loc-offset.mir index a6c4766830d..aa4a678e625 100644 --- a/llvm/test/DebugInfo/X86/debug-loc-offset.mir +++ b/llvm/test/DebugInfo/X86/debug-loc-offset.mir @@ -32,7 +32,7 @@ # Checking that we have two compile units with two sets of high/lo_pc. # CHECK: .debug_info contents # CHECK: DW_TAG_compile_unit -# CHECK: DW_AT_low_pc {{.*}} (0x0000000000000018 ".text") +# CHECK: DW_AT_low_pc {{.*}} (0x0000000000000020 ".text") # CHECK: DW_AT_high_pc # # CHECK: DW_TAG_subprogram @@ -42,8 +42,8 @@ # CHECK: DW_TAG_formal_parameter # CHECK-NOT: DW_TAG # CHECK: DW_AT_location [DW_FORM_sec_offset] ({{.*}} -# CHECK-NEXT: [0x00000021, 0x0000002f): DW_OP_breg0 EAX+0, DW_OP_deref -# CHECK-NEXT: [0x0000002f, 0x0000005b): DW_OP_breg5 EBP-8, DW_OP_deref, DW_OP_deref +# CHECK-NEXT: [0x00000029, 0x00000037): DW_OP_breg0 EAX+0, DW_OP_deref +# CHECK-NEXT: [0x00000037, 0x00000063): DW_OP_breg5 EBP-8, DW_OP_deref, DW_OP_deref # CHECK-NEXT: DW_AT_name [DW_FORM_strp]{{.*}}"a" # # CHECK: DW_TAG_variable @@ -177,7 +177,7 @@ ... --- name: _Z3bari -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: stackSize: 8 @@ -212,7 +212,7 @@ body: | ... --- name: _Z3baz1A -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: stackSize: 28 diff --git a/llvm/test/DebugInfo/X86/dw_op_minus.mir b/llvm/test/DebugInfo/X86/dw_op_minus.mir index 21c8c5a9424..c5b9ffcd3ee 100644 --- a/llvm/test/DebugInfo/X86/dw_op_minus.mir +++ b/llvm/test/DebugInfo/X86/dw_op_minus.mir @@ -83,7 +83,7 @@ ... --- name: f -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: stackSize: 24 diff --git a/llvm/test/DebugInfo/X86/live-debug-values-constprop.mir b/llvm/test/DebugInfo/X86/live-debug-values-constprop.mir index 086f664e19a..57405786ef2 100644 --- a/llvm/test/DebugInfo/X86/live-debug-values-constprop.mir +++ b/llvm/test/DebugInfo/X86/live-debug-values-constprop.mir @@ -95,7 +95,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: [] liveins: @@ -158,7 +158,7 @@ body: | ... --- name: bar -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: [] liveins: @@ -222,7 +222,7 @@ body: | ... --- name: baz -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: [] liveins: @@ -286,7 +286,7 @@ body: | ... --- name: qux -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: [] liveins: diff --git a/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir b/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir index 0634f1f6e3f..9d6ec9f4eca 100644 --- a/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir +++ b/llvm/test/DebugInfo/X86/live-debug-vars-dse.mir @@ -88,7 +88,7 @@ ... --- name: f -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/DebugInfo/X86/pr19307.mir b/llvm/test/DebugInfo/X86/pr19307.mir index dd6c9869afe..3815b6f8b3e 100644 --- a/llvm/test/DebugInfo/X86/pr19307.mir +++ b/llvm/test/DebugInfo/X86/pr19307.mir @@ -144,7 +144,7 @@ ... --- name: _Z11parse_rangeRyS_Ss -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } |
