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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
define <64 x i8> @test_add_v64i8(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
%ret = add <64 x i8> %arg1, %arg2
ret <64 x i8> %ret
}
define <32 x i16> @test_add_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) #0 {
%ret = add <32 x i16> %arg1, %arg2
ret <32 x i16> %ret
}
define <16 x i32> @test_add_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) #1 {
%ret = add <16 x i32> %arg1, %arg2
ret <16 x i32> %ret
}
define <8 x i64> @test_add_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) #1 {
%ret = add <8 x i64> %arg1, %arg2
ret <8 x i64> %ret
}
attributes #0 = { "target-features"="+avx512f,+avx512bw" }
attributes #1 = { "target-features"="+avx512f" }
...
---
name: test_add_v64i8
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; ALL-LABEL: name: test_add_v64i8
; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
; ALL: [[VPADDBZrr:%[0-9]+]]:vr512 = VPADDBZrr [[COPY]], [[COPY1]]
; ALL: $zmm0 = COPY [[VPADDBZrr]]
; ALL: RET 0, implicit $zmm0
%0(<64 x s8>) = COPY $zmm0
%1(<64 x s8>) = COPY $zmm1
%2(<64 x s8>) = G_ADD %0, %1
$zmm0 = COPY %2(<64 x s8>)
RET 0, implicit $zmm0
...
---
name: test_add_v32i16
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; ALL-LABEL: name: test_add_v32i16
; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
; ALL: [[VPADDWZrr:%[0-9]+]]:vr512 = VPADDWZrr [[COPY]], [[COPY1]]
; ALL: $zmm0 = COPY [[VPADDWZrr]]
; ALL: RET 0, implicit $zmm0
%0(<32 x s16>) = COPY $zmm0
%1(<32 x s16>) = COPY $zmm1
%2(<32 x s16>) = G_ADD %0, %1
$zmm0 = COPY %2(<32 x s16>)
RET 0, implicit $zmm0
...
---
name: test_add_v16i32
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; ALL-LABEL: name: test_add_v16i32
; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
; ALL: [[VPADDDZrr:%[0-9]+]]:vr512 = VPADDDZrr [[COPY]], [[COPY1]]
; ALL: $zmm0 = COPY [[VPADDDZrr]]
; ALL: RET 0, implicit $zmm0
%0(<16 x s32>) = COPY $zmm0
%1(<16 x s32>) = COPY $zmm1
%2(<16 x s32>) = G_ADD %0, %1
$zmm0 = COPY %2(<16 x s32>)
RET 0, implicit $zmm0
...
---
name: test_add_v8i64
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; ALL-LABEL: name: test_add_v8i64
; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
; ALL: [[VPADDQZrr:%[0-9]+]]:vr512 = VPADDQZrr [[COPY]], [[COPY1]]
; ALL: $zmm0 = COPY [[VPADDQZrr]]
; ALL: RET 0, implicit $zmm0
%0(<8 x s64>) = COPY $zmm0
%1(<8 x s64>) = COPY $zmm1
%2(<8 x s64>) = G_ADD %0, %1
$zmm0 = COPY %2(<8 x s64>)
RET 0, implicit $zmm0
...
|
