diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir')
| -rw-r--r-- | llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir index 168bc53309d..f6a6598a76a 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir @@ -10,7 +10,7 @@ ... --- name: load1_s8_to_zextLoad1_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -32,7 +32,7 @@ body: | ... --- name: load2_s16_to_zextLoad2_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: load1_s8_to_sextLoad1_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true @@ -76,7 +76,7 @@ body: | ... --- name: load2_s16_to_sextLoad2_s32 -alignment: 2 +alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true |
