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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# Verify that we get FCMPSri when we compare against 0.0 and that we get
# FCMPSrr otherwise.
...
---
name: zero
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $s0, $s1
; CHECK-LABEL: name: zero
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
%3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
$s0 = COPY %3(s32)
RET_ReallyLR implicit $s0
...
---
name: notzero
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.1:
liveins: $s0, $s1
; CHECK-LABEL: name: notzero
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 112
; CHECK: FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = COPY $s1
%2:fpr(s32) = G_FCONSTANT float 1.000000e+00
%3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
$s0 = COPY %3(s32)
RET_ReallyLR implicit $s0
|
