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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
; ModuleID = 'sitofp_legal.ll'
source_filename = "sitofp.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone uwtable
define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 {
entry:
%conv = sitofp i32 %a to float
ret float %conv
}
; Function Attrs: norecurse nounwind readnone uwtable
define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 {
entry:
%conv = sitofp i64 %a to float
ret float %conv
}
; Function Attrs: norecurse nounwind readnone uwtable
define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 {
entry:
%conv = sitofp i32 %a to double
ret double %conv
}
; Function Attrs: norecurse nounwind readnone uwtable
define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 {
entry:
%conv = sitofp i64 %a to double
ret double %conv
}
attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
!llvm.module.flags = !{!0}
!llvm.ident = !{!1}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{!"clang version 7.0.0"}
...
---
name: int32_to_float
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1.entry:
liveins: $edi
; CHECK-LABEL: name: int32_to_float
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]]
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SSrr]]
; CHECK: $xmm0 = COPY [[COPY1]]
; CHECK: RET 0, implicit $xmm0
%0:gpr(s32) = COPY $edi
%1:vecr(s32) = G_SITOFP %0(s32)
%2:vecr(s128) = G_ANYEXT %1(s32)
$xmm0 = COPY %2(s128)
RET 0, implicit $xmm0
...
---
name: int64_to_float
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1.entry:
liveins: $rdi
; CHECK-LABEL: name: int64_to_float
; CHECK: liveins: $rdi
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; CHECK: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]]
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SSrr]]
; CHECK: $xmm0 = COPY [[COPY1]]
; CHECK: RET 0, implicit $xmm0
%0:gpr(s64) = COPY $rdi
%1:vecr(s32) = G_SITOFP %0(s64)
%2:vecr(s128) = G_ANYEXT %1(s32)
$xmm0 = COPY %2(s128)
RET 0, implicit $xmm0
...
---
name: int32_to_double
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1.entry:
liveins: $edi
; CHECK-LABEL: name: int32_to_double
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SDrr]]
; CHECK: $xmm0 = COPY [[COPY1]]
; CHECK: RET 0, implicit $xmm0
%0:gpr(s32) = COPY $edi
%1:vecr(s64) = G_SITOFP %0(s32)
%2:vecr(s128) = G_ANYEXT %1(s64)
$xmm0 = COPY %2(s128)
RET 0, implicit $xmm0
...
---
name: int64_to_double
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
body: |
bb.1.entry:
liveins: $rdi
; CHECK-LABEL: name: int64_to_double
; CHECK: liveins: $rdi
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; CHECK: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]]
; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SDrr]]
; CHECK: $xmm0 = COPY [[COPY1]]
; CHECK: RET 0, implicit $xmm0
%0:gpr(s64) = COPY $rdi
%1:vecr(s64) = G_SITOFP %0(s64)
%2:vecr(s128) = G_ANYEXT %1(s64)
$xmm0 = COPY %2(s128)
RET 0, implicit $xmm0
...
|
