| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added support for REM | Rodrigo Alejandro Melo | 2017-12-01 | 1 | -1/+1 |
| | | | | | | It works as MOD. MOD is bad implemented, but useful when the two operand has the same sign. | ||||
| * | Added support to entity instantiations | Rodrigo Alejandro Melo | 2017-11-28 | 1 | -0/+7 |
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| * | Align the prototypes for dsp in dsp and genericmap | Larry Doolittle | 2017-11-20 | 1 | -2/+2 |
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| * | Simple fix to genericmap example | Larry Doolittle | 2017-11-18 | 1 | -2/+2 |
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| * | Changes on genericmap due to unsupported port assignment | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+2 |
| | | | | | This unsupported port assignament and one unsupported type of instantiation were added to todo.vhd. | ||||
| * | Examples were corrected according to GHDL complains | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+2 |
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| * | Rework some examples so resulting Verilog compiles | Larry Doolittle | 2017-11-10 | 1 | -3/+22 |
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| * | Fixes in examples and translated examples to avoid some complains of iVerilog | Rodrigo Alejandro Melo | 2017-02-19 | 1 | -4/+4 |
| | | | | | | 'test' was repeated as entity/module name 'config' was used as port name and is a reserved word in Verilog. | ||||
| * | Added analysis of examples with GHDL | Rodrigo Alejandro Melo | 2017-02-14 | 1 | -1/+1 |
| | | | | | | | | | Some examples were corrected according GHDL complains. Corresponding traslated_examples were modified. Use of synopsys libraries was removed. Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned'). The problem was comented. | ||||
| * | vhd2vl-2.2 | Larry Doolittle | 2015-09-20 | 1 | -0/+79 |
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index : vhdl2vl | |
| vhdl2vl | Raptor Computing Systems |
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