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| author | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-19 13:07:50 -0300 |
|---|---|---|
| committer | Rodrigo Alejandro Melo <rodrigomelo9@gmail.com> | 2017-02-19 13:07:50 -0300 |
| commit | 9e31f0b1ef46e3233b8fd5ec0c0d45363051bdb8 (patch) | |
| tree | 0055d2f9e9a2a2f12c5a107e8a2599e60d308d68 /examples/genericmap.vhd | |
| parent | 1ac8bf5886ade040002ff53e4d460fe4010140eb (diff) | |
| download | vhdl2vl-9e31f0b1ef46e3233b8fd5ec0c0d45363051bdb8.tar.gz vhdl2vl-9e31f0b1ef46e3233b8fd5ec0c0d45363051bdb8.zip | |
Fixes in examples and translated examples to avoid some complains of iVerilog
'test' was repeated as entity/module name
'config' was used as port name and is a reserved word in Verilog.
Diffstat (limited to 'examples/genericmap.vhd')
| -rw-r--r-- | examples/genericmap.vhd | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd index 1132554..33d9363 100644 --- a/examples/genericmap.vhd +++ b/examples/genericmap.vhd @@ -1,6 +1,6 @@ LIBRARY IEEE; USE IEEE.std_logic_1164.all; -entity test is +entity genericmap is generic( rst_val : std_logic := '0'; thing_size: integer := 201; @@ -13,7 +13,7 @@ port( we : in std_logic; pixel_in : in std_logic_vector(7 downto 0); pix_req : in std_logic; - config, bip : in std_logic; + bip : in std_logic; a, b : in std_logic_vector(7 downto 0); c, load : in std_logic_vector(7 downto 0); pack : in std_logic_vector(6 downto 0); @@ -27,8 +27,8 @@ port( complex : out std_logic_vector(23 downto 0); eno : out std_logic ); -end test; -architecture rtl of test is +end genericmap; +architecture rtl of genericmap is component dsp generic( |
