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authorRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-12-01 17:51:10 -0300
committerRodrigo Alejandro Melo <rmelo@inti.gob.ar>2017-12-01 17:51:10 -0300
commit5857951169357d6ad64aac9dee3f864d4fddf65b (patch)
tree964e52203ec7d38ec86aa167f2628cf35d09ef25 /examples/genericmap.vhd
parent4aa6f8e07914cb1aa8cde5da5e3512c0f717f737 (diff)
downloadvhdl2vl-5857951169357d6ad64aac9dee3f864d4fddf65b.tar.gz
vhdl2vl-5857951169357d6ad64aac9dee3f864d4fddf65b.zip
Added support for REM
It works as MOD. MOD is bad implemented, but useful when the two operand has the same sign.
Diffstat (limited to 'examples/genericmap.vhd')
-rw-r--r--examples/genericmap.vhd2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 876f159..3038f88 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -3,7 +3,7 @@ USE IEEE.std_logic_1164.all;
entity genericmap is
generic(
rst_val : std_logic := '0';
- thing_size: integer := 201;
+ thing_size: integer := 201 rem 2;
bus_width : integer := 201 mod 32);
port(
clk, rstn : in std_logic;
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