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author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-20 07:19:45 -0800 |
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committer | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2017-11-20 07:19:45 -0800 |
commit | 49ff6f12d6365de2fd728c63c55c3989b4437a78 (patch) | |
tree | 7416ba3bde662a0a7f5336dc55f91a6d46d84b6f /examples/genericmap.vhd | |
parent | 8fc08b52dcdbd14b8d653fde3b4d87cd63918546 (diff) | |
download | vhdl2vl-49ff6f12d6365de2fd728c63c55c3989b4437a78.tar.gz vhdl2vl-49ff6f12d6365de2fd728c63c55c3989b4437a78.zip |
Align the prototypes for dsp in dsp and genericmap
Diffstat (limited to 'examples/genericmap.vhd')
-rw-r--r-- | examples/genericmap.vhd | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd index 39db71e..c5275ba 100644 --- a/examples/genericmap.vhd +++ b/examples/genericmap.vhd @@ -34,14 +34,14 @@ architecture rtl of genericmap is generic( rst_val : std_logic := '0'; thing_size: integer := 201; - bus_width : integer := 22); + bus_width : integer := 24); port( -- Inputs clk, rstn : in std_logic; en, start : in std_logic; param : in std_logic_vector(7 downto 0); addr : in std_logic_vector(2 downto 0); - din : in std_logic_vector(25 downto 0); + din : in std_logic_vector(bus_width-1 downto 0); we : in std_logic; memdin : out std_logic_vector(13 downto 0); -- Outputs |