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* PM HWP: Fix bug in stop clock procedure that effects mpiplPrasad Bg Ranganath2019-02-281-2/+6
| | | | | | | | | | | | | | | CQ:SW455762 Change-Id: I43080c575355499cddf19b6ee094e23c94445e66 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71581 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71596 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM:Some more cleanups in update_ec_eq procedure for core unit xstop casePrasad Bg Ranganath2018-08-311-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | - Enabled EX check. even if it's EQ is functional - one more check of clock power off which is required for mpipl case. - had one bug during l2/l3 stop clock which fixes status bit update. Actually clock was stopped but the status bit was not set in EQ_CLOCK_STAT register. Key_Cronus_Test=PM_REGRESS Change-Id: I7e8dbea00235ade5a692198dde7c2e6758809b9f CQ:SW443537 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65360 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65364 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Prevent Core-L2 Quiesce from removing PM_EXIT upon SPWUYue Du2018-08-011-1/+11
| | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I34f08519d2c86fec2f0ee0feb96a62bd826e31fa CQ: SW440301 cmvc-prereq: 1063483 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61438 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62502 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: remove chiplet enable drop in core_poweron for multicast scomYue Du2018-07-181-4/+1
| | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I388c81cc1af356231daa4a11702a3a84dcc222c9 CQ: SW437797 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62302 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62326 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* mask core SPATTN bit used for core checkstop handshakeJoe McGill2018-06-051-0/+2
| | | | | | | | | | | | | | Change-Id: I9c0a7224c3880ab40bb9111d8f66449912029e2f CQ: SW431474 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59707 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59713 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM_SPWKUP: Clear wakeup notify select bit to enable auto special wakeupGreg Still2018-02-221-1/+11
| | | | | | | | | | | | | | | | | | | | - Deal with Hostboot cores coming out of istep 4 Key_Cronus_Test=PM_REGRESS Change-Id: Ie990d82eed0cb5ab3c71752a557d2f5b197d5642 CQ:SW412666 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54140 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54166 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cache/Core stop clocks: add shut down of Power Management to remove contentionsAmit Tendolkar2017-12-071-2/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ported changes from https://ralgit01.raleigh.ibm.com/gerrit1/#/c/44781/25 to simplify auto mirror conflicts and reuse existing SBE HWP files - Halt SGPE, PGPE and CMEs assocatiated within the targeted EQ - Clear the PCB atomic lock that may be in place by SGPE - Add core stopclocks changes - Fixed cache stop clocks XML callout - Fix atomic lock library dependencies - Only enable function on DD2 - Halt PPE only if not already in halt - Enhance PPE Halt FFDC Key_Cronus_Test=PM_REGRESS Change-Id: Id6c11176d222213bf1a01b91cade41de989f04c6 RTC: 180317 CQ: SW406569 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50415 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50420 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW415883 applies to NDD2.1, Add JellyVector WAT, add HW422495, add HW421831Nick Klazynski2017-10-121-1/+1
| | | | | | | | | | | | | | | | | | - WAT replaces original workaround for HW419818; two dials removed Change-Id: I540aead6556278a1da3774eba2d96cb685c4e3c1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47181 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47958 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_thread_control -- remove threads_running check from sreset, start code pathsJoe McGill2017-10-041-66/+0
| | | | | | | | | | | | | | | | | | | | | After a write to DIRECT_CONTROLS, the targeted thread will start executing instructions, which may include STOP. Future polling of the RAS_STATUS register is not guaranteed to satisfy the threads_running check (by the time RAS_STATUS is polled the thread may be idle again) Change-Id: Ie3628149cef5089fb635256df5a25f08dbd828dc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47069 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47076 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM Level 3 for multiple proceduresAmit Kumar2017-09-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit itends to make following HWP level 3 ready - p9_pm_pfet_control - p9_pm_pfet_init - p9_common_poweronoff - p9_hcd_core_poweron - p9_hcd_cache_chiplet_reset - p9_hcd_cache_poweron - p9_pm_set_homer_bar - p9_query_stop_state It also removes inclusion p9_common_poweronoff.C in C files of many HWP. Change-Id: I28a14ce4fe99630c4aa4a9044c2653763bbe35c5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41795 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41797 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Synchronous stopclk procedure for QuadSoma BhanuTej2017-08-162-29/+45
| | | | | | | | | | | | | | | | | | | Change-Id: Id31daf8c02b74d979927540346a3cef5f88768be RTC: 175615 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34935 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34939 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L3 Update - p9_thread_control HWPThi Tran2017-08-072-245/+195
| | | | | | | | | | | | | | | | Change-Id: If97d1f54a1e5d8514d56969458713bcff51dc399 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43376 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43379 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Istep4: procedures upgrade to level3Yue Du2017-07-2026-325/+222
| | | | | | | | | | | | | Change-Id: I281a7ba91a13f4694de78d65edb8a9ea65e4756e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40733 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40740 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* updates for thread control, ramming with STOP enabledJoe McGill2017-07-191-64/+33
| | | | | | | | | | | | | | | | | | | | | | | | remove pre-stop checks in p9_thread_control_stop, just attempt stop and confirm final expected state is reached: - after special wakeup from STOP2, existing threads_stopped check will fail given that the thread does not reach maintenance mode - the threads_running check will also fail assert ram_active in ram_setup function, if the thread is found to be inactive at the time ram is requested Change-Id: Iad8fd9e8a14395102b6c1b31d6595300a2da111f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42674 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42676 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Delete deprecated attributesGreg Still2017-07-141-4/+4
| | | | | | | | | | | | | | | | | | | | - Complete the move to platform SYSTEM_*_DISABLED and HWP *_ENABLED attributes - Added VDM DPLL response attribute to CME header mapping - Updated review comments Change-Id: If8f8e42fd94825623315e8a7c28105cca8c8c8b2 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42918 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42919 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L3 update -- p9_sbe_instruct_startThi Tran2017-06-232-12/+11
| | | | | | | | | | | | | | | | Change-Id: I2c501b01f8bf819f2610dcf55a9225bb70e19c18 RTC:139623 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42110 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42119 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Pstate: Remove legacy VDM codeChristopher M. Riedl2017-05-122-10/+3
| | | | | | | | | | | | | | | | | | | - Remove legacy VDM code in preparation for actual VDM enablement commit - VDM enablement only occurs during istep15 - Does not introduce any inter-platform dependencies Change-Id: Ia46661f6133e2556bee0464a95c7109658a86beb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40185 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40221 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* IPL: Add global checkstop FIR check in Istep4Yue Du2017-04-281-14/+34
| | | | | | | | | | | | | | Change-Id: I01071130bcb020c020b7af6a72b0f736a3a07f69 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39241 Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39242 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Include p9_ring_id.h or p9_ringId.HKahn Evans2017-03-231-0/+1
| | | | | | | | | | | | | | | | Prepare for it no longer being included in fapi2_hw_access.H Change-Id: I9d95f86e9a63810b0b96a0a84415d0349816e981 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38248 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38252 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Inclusion of p9_ring_id.hKahn Evans2017-03-211-0/+1
| | | | | | | | | | | | | | | | | Prepare for it no longer being included in fapi2_hw_access.H Change-Id: I0d99c658ed4b3319d40d1843d08d0b6b834fbf1e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37974 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37980 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Core Init additions to put ABIST engines in parallel mode for Nimbus DD1.0Thi Tran2017-03-211-2/+22
| | | | | | | | | | | | | | | | | | | | CMVC-Prereq:1019352 RTC:167284 Change-Id: I167c63950f72eb0446e3dd746ebd1e12adfb9f69 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36962 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36965 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* IPL Only: Drop chiplet fence in scomcust instead of startclocksYue Du2017-03-033-45/+39
| | | | | | | | | | | | Change-Id: I4f60bdfa33dc7752851411155d97c0a2d913ef99 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36031 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36143 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* IPL/Stop: Assert ABIST_SRAM_MODE_DC to support ABIST RecoveryYue Du2017-02-282-0/+8
| | | | | | | | | | | | | | | Change-Id: I4465535c32e3cde8e8e2f0f3a13bb1d66d1f7614 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36728 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36730 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW399609: DD1 changing core/nest hang limit or hang pulse dividerYue Du2017-02-241-11/+44
| | | | | | | | | | | | | | Change-Id: I580cd70ce3315ea3f2aeb274279a89375f02b05d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36375 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36382 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_thread_control poll more than once for thread running.Ben Gass2017-02-241-3/+10
| | | | | | | | | | | | | | | | | Based on HW403758 the L2 can block threads from sreset for a period of time. Change-Id: I704df2e970d9496257c565b99995887696ff7d2a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36594 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36688 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert "Hcode: Drop chiplet fence after scominit and scomcust hwp."YUE DU2017-02-093-33/+44
| | | | | | | | | | | | | | This reverts commit 8da1c05a2580a96b3cc4a46b8cd25ecce06ee208. Change-Id: I6c23f3a6dadc1b55a3df8f2d879fe225f227a639 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36067 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36157 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Hcode: Drop chiplet fence after scominit and scomcust hwp.Yue Du2017-02-063-46/+35
| | | | | | | | | | | | | | Change-Id: I88e9f9087e9877b63cb9eadeda99ad6cc286485c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35758 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: JAMES DEZELLE <jdezelle@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35766 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Istep4: clean up istep4 todo items and mark them with RTCYue Du2017-01-318-32/+32
| | | | | | | | | | | | | | | Change-Id: I6ebe062043fe8d7d036ec5c3a32cf2115fb0fc95 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34689 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34690 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SW375288: Reads to C_RAS_MODEREG causes SPR corruptionNick Klazynski2017-01-111-13/+19
| | | | | | | | | | | | | | | Change-Id: Idf1c1e78657bddb1747dc6e72b0af67afad26a91 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34570 Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34571 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* HCODE: Drop TLBIE Quiesce after initfile scan it to 1Yue Du2016-12-201-2/+2
| | | | | | | | | | | | | Change-Id: I279dad3189835157deb5db14545376cd8f896fb4 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34027 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34028 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
* update core internal/external hang timeoutsJoe McGill2016-12-201-0/+11
| | | | | | | | | | | | | | | | | update base pervasive hang pulse scale core (internal) / nest (external) hang dividers resultant timeouts measured at 1866 MHz: ~50ms internal ~1.2s external Change-Id: I747a059c1f62c334114f9a5324c6f727364c76ac Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33374 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33375 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Istep4: Shouldn't set group_id in cache-contained modeYue Du2016-12-201-7/+11
| | | | | | | | | | | | | Change-Id: I44066d66d85e351e5a9f19571caff35d0fad7d52 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32693 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32718 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP Image updatesYue Du2016-11-212-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is pending to be regressed and merged. Thus, freeze puting new change feature in unless necessary fix to existing features. 1) add starting ANEP clock and drop ANEP regional fence before starting DPLL clock 2) change trace level to 1 by default change trace level 1 to only print tiny traces trace level 2 will print variable debug info trace level 3 will print all traces 3) use self restore address from header instead of hardcoded 4) enable dpll lock check when in lab 5) finish up lco settings in sgpe code 6) DTS enablement in stop/istep code 7) skip cache power off if hostAttn or localXstop 8) istep4 set special wakeup, sgpe remove when ready 9) disable dpll lock check as still work in progress 10)rebase 11)fix jenkins 12)fix db1 workaround on OR/CLR address 13)can write db1 base address directly instead of read first 14)fix self restore address fetch 15)clear pig type2/3/6 pending in sgpe setup 16)move hostAttn/localXstop read before stopclocks 17)fix typo in 16) 18)fix getscom(hostAttn/localXstop) 19)fix hrmor[13:42] Change-Id: Ibde32271db0543661c426d8eed8531ba6312c6e5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32514 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32516 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-214-19/+37
| | | | | | | | | | | | | | | | | | | | | | | changes in this commit: 1) enable dpll lock checking in non-sim envrionment 2) change FAPI_DBG lines on set/reset sdis_n ops as removing prints saying they are DD1 only workaround due to they are permenant steps now 3) add missing content of p9_hcd_core_dcc_skewadjust 4) add DD2 sram_enable support (NOOP for DD1) Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719 Reviewed-by: Joseph E. Dery <dery@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31810 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Thread Control Stop precedure updateRaja Das2016-10-281-47/+60
| | | | | | | | | | | | | | RTC: 163286 Change-Id: Ideed55453791c461e10dc731aab0409d5b7cccad Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31604 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31607 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* p9_hcd_core_startclocks -- set CPLT_CONF0 system/group/chip ID fieldsJoe McGill2016-10-261-0/+19
| | | | | | | | | | | | | | | | required to configure the PIR SPR correctly on multi-socket systems Change-Id: Iadfcd5bd52e1ea1914de98c6a76e36a9f5d2e36a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31795 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31798 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Istep4: add enable auto special wakeup after core is upYue Du2016-10-261-0/+6
| | | | | | | | | | | | | | | Change-Id: I165c99b16998b1c4961008db4bcf054330209e8c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31566 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31571 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* cache/core/l2_stopclocks updatesYue Du2016-10-261-24/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | patchset 1: skip l2_stopclocks if ex_select is 0 patchset 2: check power state before execute hwp patchset 3: fix syntax typos from patch 2 update patchset 4: add chiplet accessibility check patchset 5: add possible counter to CME PCBMUX patchset 6: add skipping message on check patchset 7: change polling timout method patchset 8: add a missing comma patchset 9: fix ffdc patchset 10:roll back cme pcbmux counter until check to ensure cme accessibility patchset 11:rebased patchset 12:initial checkin of ppe state handling patchset 13:checkin new clk_ctrl_state procedure patchset 14:add attribute xml for new procedure patchset 15:fix calling the p9_common_clk_ctrl_state patchset 16:Matt rebase patchset 17:Warning instead of fail with error on check delete common C file, include only header Change-Id: I14c9480ac0931ac7f8b456f193148ceb3b939947 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28808 Dev-Ready: YUE DU <daviddu@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30365 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cleaned old makefilesSachin Gupta2016-10-152-115/+0
| | | | | | | | Change-Id: Iabcd4700c79a9542e70ab341d52a4c4f9090b99e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31293 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW390253: change core scan ratio to 2:1 as clock controller is 2:1Yue Du2016-10-141-2/+5
| | | | | | | | | | | | | | | Change-Id: Ib98b02495e189a035e464a5d0ced942a02e0b1ae Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31184 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31188 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Stop Clocks for MPIPL (Core & Cache(EQ))Raja Das2016-10-061-0/+1
| | | | | | | | | | | | RTC: 156382 Change-Id: Ib3e8c29467aa7d3b6b85286e6f5ce154f0f28ad6 RTC: 156382 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29555 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Core/Initfile: remove cache contained condtions on core-cc/l2 quiescesYue Du2016-10-061-2/+1
| | | | | | | | | | | | | | Change-Id: I4de12980ca78d3d48a9c3381e240a9355f2667e7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30696 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30698 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Interrupts must be blocked the entire time the thread is stopped.Nick Klazynski2016-10-052-32/+44
| | | | | | | | | | | | | | | | | - Instead of just blocking interrupts during the actual step operation, we should have blocked the entire time the thread is stopped. Change-Id: Ie3006a8882ad996ef62290aeae7103286211ef1f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30186 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30189 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* SBE Quiesce Implementation for FIFO/PSURaja Das2016-09-301-2/+5
| | | | | | | | | | Change-Id: I25807d8114ed359347e842e2ca15d64f912865fb RTC: 149642 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29365 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* move C_PPM_SSHSRC setup from p9_hcd_core_scominit to p9_hcd_core_startclocksJoe McGill2016-09-222-3/+6
| | | | | | | | | | | | | | | Change-Id: Ibfc344ce1b12f1c12a62bd23269f52dbec8d4380 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29999 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30000 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-8/+2
| | | | | | | | | | | | | | | | | | | Change-Id: I346f10136e9621ea06e381cfad2a2b903cb2bd64 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29834 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29836 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com>
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2016-09-201-1/+133
| | | | | | | | | | | | | | | Change-Id: I2ff90191b9a9e60b71adf5fef59dc162b3be2cd2 Original-Change-Id: Ie4bce2bcaf0ffb2d1e57370312c4536356b62efc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27338 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29920 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* CORE/CACHE: add Level1 cache/l2/core stopclocks proceduresYue Du2016-09-202-0/+126
| | | | | | | | | | | | | | | Change-Id: I7fbeb38d364730ccf308b62e139b3fce40642750 Original-Change-Id: Id407ffa51ea9a7fb9a0056a7faaf1e33e4433e50 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26276 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29918 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update file headersSachin Gupta2016-09-1631-31/+31
| | | | | | | | Change-Id: Icdd7460d8e3213f9bbd3d52e7825242bc59fc9e9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29825 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_hcd_core_scominit -- invoke p9.core.scom.initfileJoe McGill2016-09-111-1/+13
| | | | | | | | | | | | Change-Id: Iab52ed03aa71abe289dd652a810e159b462d5e67 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29282 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29285 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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