Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup

changes in this commit:

1) enable dpll lock checking in non-sim envrionment
2) change FAPI_DBG lines on set/reset sdis_n ops as
   removing prints saying they are DD1 only workaround
   due to they are permenant steps now
3) add missing content of p9_hcd_core_dcc_skewadjust
4) add DD2 sram_enable support (NOOP for DD1)

Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719
Reviewed-by: Joseph E. Dery <dery@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31810
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

4 files changed, 37 insertions, 19 deletions

diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
index 6145ad1a..47780ffb 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
@@ -75,8 +75,7 @@ p9_hcd_core_arrayinit(
         i_target.getParent<fapi2::TARGET_TYPE_PERV>();
 #endif
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
+    FAPI_DBG("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
 
 #ifndef P9_HCD_STOP_SKIP_ARRAYINIT
@@ -109,8 +108,7 @@ p9_hcd_core_arrayinit(
 
 #endif
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround");
+    FAPI_DBG("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
     FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));
 
 //#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT)
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
index e589933b..f4bf3ba6 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
@@ -191,6 +191,14 @@ p9_hcd_core_chiplet_reset(
     FAPI_DBG("Assert vdm enable via CPPM_VDMCR[0]");
     FAPI_TRY(putScom(i_target, C_PPM_VDMCR_OR, MASK_SET(0)));
 
+    // content of p9_hcd_core_dcc_skewadjust below:
+
+    FAPI_DBG("Drop core DCC bypass via NET_CTRL[1]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL1_WAND, MASK_UNSET(1)));
+
+    FAPI_DBG("Drop core progdly bypass(skewadjust) via NET_CTRL1[2]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL1_WAND, MASK_UNSET(2)));
+
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_core_chiplet_reset");
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
index c44e6a4d..deafdd57 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
@@ -93,6 +93,7 @@ p9_hcd_core_startclocks(
     uint8_t                                     l_attr_chip_unit_pos;
     uint8_t                                     l_attr_system_ipl_phase;
     uint8_t                                     l_attr_runn_mode;
+    uint8_t                                     l_attr_sdisn_setup;
     fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
         i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
     fapi2::Target<fapi2::TARGET_TYPE_EQ>        l_quad =
@@ -101,16 +102,21 @@ p9_hcd_core_startclocks(
         i_target.getParent<fapi2::TARGET_TYPE_PERV>();
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip,
+                           l_attr_sdisn_setup));
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID,        l_chip,
+                           l_attr_group_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID,         l_chip,
+                           l_attr_chip_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID,       l_chip,
+                           l_attr_system_id));
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RUNN_MODE,        l_sys,
                            l_attr_runn_mode));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys,
                            l_attr_system_ipl_phase));
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID,  l_chip,
-                           l_attr_group_id));
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID,   l_chip,
-                           l_attr_chip_id));
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip,
-                           l_attr_system_id));
+
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,    l_perv,
                            l_attr_chip_unit_pos));
     l_attr_chip_unit_pos = (l_attr_chip_unit_pos -
@@ -127,9 +133,11 @@ p9_hcd_core_startclocks(
         FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(5)));
     }
 
-    /// @todo add DD1 attribute control
-    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
-    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
+    if (l_attr_sdisn_setup)
+    {
+        FAPI_DBG("DD1 ONLY: Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
+        FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
+    }
 
     FAPI_DBG("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]");
     FAPI_TRY(getScom(i_target, C_OPCG_ALIGN, l_data64));
@@ -284,10 +292,7 @@ p9_hcd_core_startclocks(
                          EX_0_CME_SCOM_SICR_CLEAR : EX_1_CME_SCOM_SICR_CLEAR,
                          (BIT64(6 + (l_attr_chip_unit_pos % 2)) |
                           BIT64(8 + (l_attr_chip_unit_pos % 2)))));
-    }
 
-    if (!l_attr_runn_mode)
-    {
         FAPI_DBG("Drop auto special wakeup disable via CME_SCOM_LMCR[12/13]");
         FAPI_TRY(putScom(l_quad,
                          (l_attr_chip_unit_pos < 2) ?
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
index 1aaa7cd5..54805273 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
@@ -75,9 +75,14 @@ p9_hcd_core_stopclocks(
     uint32_t                                       l_loops1ms;
     uint8_t                                        l_attr_chip_unit_pos;
     uint8_t                                        l_attr_vdm_enable;
+    uint8_t                                        l_attr_sdisn_setup;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     auto  l_quad = i_target.getParent<fapi2::TARGET_TYPE_EQ>();
     auto  l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    auto  l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip,
+                           l_attr_sdisn_setup));
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE,       l_sys,
                            l_attr_vdm_enable));
@@ -221,9 +226,11 @@ p9_hcd_core_stopclocks(
     FAPI_DBG("Assert regional fences via CPLT_CTRL1[4-14]");
     FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_OR, p9hcd::CLK_REGION_ALL));
 
-    /// @todo RTC158181 add DD1 attribute control
-    FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround");
-    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));
+    if (l_attr_sdisn_setup)
+    {
+        FAPI_DBG("DD1 Only: Drop sdis_n(flushing LCBES condition) vai CPLT_CONF0[34]");
+        FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));
+    }
 
     // -------------------------------
     // Disable VDM