diff options
author | Yue Du <daviddu@us.ibm.com> | 2016-11-10 16:07:17 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-11-21 20:48:41 -0500 |
commit | c7011462f76abdf9dc71b83eae677ee5f2a57644 (patch) | |
tree | 5f5f58c61f2188d76a02bf26e9bb2c9ee588cb3c /src/import/chips/p9/procedures/hwp/core | |
parent | f078f464c0fd772d8e3a1bad3201ddf98f6b66db (diff) | |
download | talos-sbe-c7011462f76abdf9dc71b83eae677ee5f2a57644.tar.gz talos-sbe-c7011462f76abdf9dc71b83eae677ee5f2a57644.zip |
STOP Image updates
This commit is pending to be regressed and merged.
Thus, freeze puting new change feature in unless
necessary fix to existing features.
1) add starting ANEP clock and
drop ANEP regional fence before starting DPLL clock
2) change trace level to 1 by default
change trace level 1 to only print tiny traces
trace level 2 will print variable debug info
trace level 3 will print all traces
3) use self restore address from header instead of hardcoded
4) enable dpll lock check when in lab
5) finish up lco settings in sgpe code
6) DTS enablement in stop/istep code
7) skip cache power off if hostAttn or localXstop
8) istep4 set special wakeup, sgpe remove when ready
9) disable dpll lock check as still work in progress
10)rebase
11)fix jenkins
12)fix db1 workaround on OR/CLR address
13)can write db1 base address directly instead of read first
14)fix self restore address fetch
15)clear pig type2/3/6 pending in sgpe setup
16)move hostAttn/localXstop read before stopclocks
17)fix typo in 16)
18)fix getscom(hostAttn/localXstop)
19)fix hrmor[13:42]
Change-Id: Ibde32271db0543661c426d8eed8531ba6312c6e5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32514
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32516
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/core')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C | 9 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C | 3 |
2 files changed, 7 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C index 29f4a2ab..976a48c0 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C @@ -68,12 +68,11 @@ p9_hcd_core_scominit( FAPI_TRY(getScom(i_target, C_SYNC_CONFIG, l_data64)); FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_SET(8))); - /// @todo set the sample pulse count (bit 6:9) - /// enable the appropriate loops - /// (needs investigation with the Perv team on the EC wiring). - FAPI_DBG("Enable DTS sampling via THERM_MODE_REG[5]"); + FAPI_DBG("Enable DTS via THERM_MODE_REG[5,6-9,20-21]"); FAPI_TRY(getScom(i_target, C_THERM_MODE_REG, l_data64)); - FAPI_TRY(putScom(i_target, C_THERM_MODE_REG, DATA_SET(5))); + // DTS sampling enable | sample pulse count | DTS loop1 enable + l_data64.setBit<5>().insertFromRight<6, 4>(0xF).insertFromRight<20, 2>(0x3); + FAPI_TRY(putScom(i_target, C_THERM_MODE_REG, l_data64)); // invoke core SCOM initfile FAPI_EXEC_HWP(l_rc, p9_core_scom, i_target); diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C index deafdd57..604692fc 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -299,6 +299,9 @@ p9_hcd_core_startclocks( EX_0_CME_SCOM_LMCR_CLEAR : EX_1_CME_SCOM_LMCR_CLEAR, (BIT64(12 + (l_attr_chip_unit_pos % 2))))); + FAPI_DBG("Assert special wakeup on hostboot core via SPWKUP_OTR[0]"); + FAPI_TRY(putScom(i_target, C_PPM_SPWKUP_OTR, MASK_SET(0))); + FAPI_DBG("Set core as ready to run in STOP history register"); FAPI_TRY(putScom(i_target, C_PPM_SSHSRC, 0)); } |