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* set OTL Err Rpt Mask Reg 0 bit 21, OTL TX ECC UE on CQ buffer read data.Ryan Black2020-01-211-1/+26
| | | | | | | | | | | | | | | Change-Id: Iacb879cf0aab5db14cee794701bdcf70df2b8dd1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89053 Reviewed-by: Thi N Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89055 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* for defect number HW476620Sheng-Hao Huang2020-01-071-0/+17
| | | | | | | | | | | | | | | Change-Id: I5188183869da97f4d4f0bb9105020d562948c031 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83724 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83795 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Replaces NVDIMM flush sequence with CCSTsung Yeung2019-11-053-188/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current design relies on the power control logic to put the nvdimm into STR. There have been several defects opened on the nvdimm failing to save due to STR not entered but no indication of the function failing to execute. Therefore, the decision has been made to leverage CCS to issue STR and assert RESETn. This gives us full control of what goes onto the bus and not have to worry about STR getting exit due to unwanted mainline traffic. The same CCS sequence has already been exercised numerous times on AC powerloss path. Change-Id: Idd422beea72ee5902674562f5834c1ac9e79fe00 CQ:SW477735 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85831 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85880 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: Modified FFDC to avoid corruption of RC in error path.Prem Shanker Jha2019-09-251-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On FSP platform, in case of some errors, HWP captures certain EX level registers. To ensure availability of such registers, FSP first attempts special wakeup. Special wakeup HWP uses FAPI_TRY in its code path. It is known that in FFDC collection path, use of FAPI_TRY leads to corruption of original FAPI2 RC. Commit removes such registers from the capture list. Key_Cronus_Test=PM_REGRESS Change-Id: I23ce8b1a8a4a61f71c7b33c1122fcfac905616c4 CQ: SW471606 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83863 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83956 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Clean up for p10 porting dependency errorsAndre Marin2019-09-251-12/+0
| | | | | | | | | | | | | | | | Change-Id: I02b8dfab08121d4ac9ffbb7dedd37f7083bf527f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81543 Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82366 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add "Not Wired" option for OPTICS_CONFIG_MODE attrsChristian Geddes2019-09-091-2/+8
| | | | | | | | | | | | | | | | | | | | | For Swift systems obus1 is not wired to anything. This is causing issues when we attempt to enable the link. If we set it to NOT_WIRED then we should avoid the problem we are seeing currently where obus1 is having the NV link enabled which is getting parity errors as soon as we enabled the obus. Change-Id: I1380388cbf9a967380c6657102a1b1ae9b266014 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82766 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J McGill <jmcgill@us.ibm.com> Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82793 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Axone int updatesAdam Hale2019-08-261-0/+17
| | | | | | | | | | | | | | | Change-Id: I6468addadd23f6f252ade88eacfd6a1fd2f47025 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82625 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Reviewed-by: Devon A Baughen <devon.baughen1@ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82635 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: Fix DB0 HangRahul Batra2019-08-261-0/+1
| | | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I706ec7b87e777b736153d5765ced0a3f6cea5d96 CQ: SW470688 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81266 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81560 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add slbv, slbe extraction to p9_ram_core procedureJenny Huynh2019-08-251-1/+13
| | | | | | | | | | | | | Change-Id: I6efe5d4f8fbb9f893a2371acd108d9d1d3002ecd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82496 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K Light <mklight@us.ibm.com> Reviewed-by: Thi N Tran <thi@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82502 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_proc_gettracearray -- updates for AxoneJoe McGill2019-08-252-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_tracearray_defs.H: - adjust value of PROC_TB_LAST_AXONE_CHIP_TARGET, to cover NPU busses only - introduce PROC_TB_LAST_AXONE_MC_TARGET, to cover OMI busses that logically associate with MC pervasive targets p9_proc_gettracearray.H: - update proc_gettracearray_target_type to return TARGET_TYPE_MC for Axone OMI busses p9_sbe_tracearray.H: - update p9_sbe_tracearray_target_type to return TARGET_TYPE_PERV for Axone OMI busses p9_proc_gettracearray_wrap.C: - add eCMD looper to determine chip type - use chip type to swizzle target type returned by proc_gettracearray_target_type from MCBIST to MC, when running on Axone or Cumulus Change-Id: I5c729385c685ed3b1aac02f1f63b2c81f3e2f0e0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82308 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Dev-Ready: Joseph J McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82361 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add workaround for gemini OMI config settingsMark Pizzutillo2019-08-151-0/+17
| | | | | | | | | | | | | | | Change-Id: I4318e5d696056a3250999248aec360ce5ea7bcd3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81320 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81325 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Axone Gemini MDI issue workaroundAdam Hale2019-08-121-0/+17
| | | | | | | | | | | | | | | | Change-Id: I3b95102ddf76610380c12f32f39464b8f80b2a07 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81448 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81481 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Axone setup changes to disable bumpy toothpaste workaroundAdam Hale2019-08-111-3/+19
| | | | | | | | | | | | | | | | Change-Id: Id8f2302b2995c2c123b1ef7d4a864ebc935efe00 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78199 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Devon A Baughen <devon.baughen1@ibm.com> Dev-Ready: Adam S Hale <adam.samuel.hale@ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78212 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Create workaround for gemini MENTERP register bugMark Pizzutillo2019-08-111-0/+17
| | | | | | | | | | | | | | | | | Bypass writes and reads to the menterp register to avoid FW bug Change-Id: I2dfc96d0408b16a22280d16e3edea3900468cfc0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81615 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81631 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Account for OMI technology in initial mcs setup for AxoneChristian Geddes2019-08-062-17/+69
| | | | | | | | | | | | | | | | | | | The scom registers that setup the memory channel's intial state get written during the SBE steps. The hwp that does this needs to be updated to account for the changes to the MCFGP0 register that happened between P9N/P9C and P9A. Change-Id: Icfa50177f9fefca3acabbbc41b60f65d280348e7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81458 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81482 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Move to long term CLSCOM workaroundAdam Hale2019-08-061-2/+1
| | | | | | | | | | | | | | | | Change-Id: I33ff7d349b63c54794bf6acf806c89d22e5d9ac0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81474 Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: Devon A Baughen <devon.baughen1@ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81486 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add PRBS training sequence to exp_omi_setupMark Pizzutillo2019-08-061-0/+18
| | | | | | | | | | | | | | | | Change-Id: I85630e3959cd95317c5026f1efaaa8062c4bbbe6 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80238 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Mark Pizzutillo <mark.pizzutillo@ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80330 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* adding iss 768 init for p9 behaviour in nmmuEmmanuel Sacristan2019-08-061-0/+17
| | | | | | | | | | | | | | | Change-Id: I41d302272200ddc37276f56e238ccab8ed768163 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81386 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Reviewed-by: JAKE C TRUELOVE <jtruelove@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81401 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Streamline the way PIB/NET are initialized between SBE and CronusJoachim Fenkes2019-07-303-73/+55
| | | | | | | | | | | | | | | | | | | | | | | | | Instead of p9_start_cbs swinging the PCB mux to PIB2PCB, do it in p9_sbe_tp_chiplet_init1. The PIBMEM repair code on the SBE does it this way already so no change is needed there. This way, even if we start the SBE but then run isteps in Cronus, both pieces of code will work correctly since they don't depend on previous steps leaving the mux in a specific state. Change-Id: I4a2bd53f813cbb0a00486effb156a3c2a7f4336a CQ: SW470122 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81162 Reviewed-by: Joseph J McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Milton D Miller <miltonm@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81191 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add Axone comment to grouping attributeDan Crowell2019-07-301-4/+4
| | | | | | | | | | | | | | | | | | Pointing out the use of MCC for grouping attribute Change-Id: I5dbd03d18ca4e9d0d6b638d8458c365809f5e68f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79460 Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79499 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Wilted Apple: Disable SMT2 prefetch for NDD2.2+, CDD1.1+, ADD1.0+Jenny Huynh2019-07-301-0/+31
| | | | | | | | | | | | | | | Change-Id: I389e779bd00ae699d2b05fda61b4aff83e386089 CQ: HW499047 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80816 Reviewed-by: Kevin F Reick <reick@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80864 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* P9A Tx Fifo Init + Init Settings UpdateChris Steffen2019-07-171-7/+0
| | | | | | | | | | | | | | | | | | | - Added Tx Fifo Init Function to Dccal - Forced rx_dc_enable_cm_coarse_en = 0 - Updated P9A Filt Pll Attribute to select BG = 0 Change-Id: I7090856ba48886fb278e65814249a0166b7fe098 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80218 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80322 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* temporary mc inits to enable wider teamAdam Hale2019-07-172-2/+20
| | | | | | | | | | | | | | | Change-Id: Ic9adb821799b3383b90b8e9feb86815c9b28f7f2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79669 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Devon A. Baughen <devon.baughen1@ibm.com> Reviewed-by: BRIANA E. FOXWORTH <befoxwor@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79874 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Hide CHTM attributes from ServerWizDan Crowell2019-06-261-0/+3
| | | | | | | | | | | | | | | | | These are lab-only attributes that should not get set by MRW xml. Change-Id: Ie0579cd33ae32a1a7dfcc2fbe59688ad8fc03bd0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77942 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77955 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Disable BAR Temporarily to prevent STR exit during nvdimm handoverTsung Yeung2019-06-242-27/+85
| | | | | | | | | | | | | | | Change-Id: Ib7e95d8aa0b77570fec9c76211e78d790f540b06 CQ:SW468134 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79219 Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79375 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* update i2c bit rate divisor for p9aJoe McGill2019-06-153-2/+29
| | | | | | | | | | | | | | | | | p9a i2cm HW changes require nest/4/2/4 programming Change-Id: Ib29c307fa2250f5096578809e3d0cb10a027086e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78640 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78664 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add missing targetType arg to ATTR_CHIP_EC_FEATURE_CORE_SMF_SETUPJenny Huynh2019-06-141-1/+1
| | | | | | | | | | | | | | | Change-Id: I01f3c04c8f1534d6557290f8852a88bbb87f3ea2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78757 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78773 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add polling after STR entry to ensure port is in STR before asserting RESETnTsung Yeung2019-06-142-1/+68
| | | | | | | | | | | | | | | | Change-Id: Ic28ca541a578daccc0b9df6d8ffa99622c9eda38 CQ:SW465520 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78505 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78869 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: WOV(OCS) HW Procedures Changes (1/2)Rahul Batra2019-06-141-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | 1st commit in the series of 2 commits for WOV(Over Current Sampling, OCS) Commit 1: WOV(OCS) HW procedures updates Commit 2: WOV(OCS) PGPE Hcode updates Key_Cronus_Test=PM_REGRESS HW-Image-Prereq: Ieabbc383d2bbbd1df8cf5a2ed5b503c860518cd8 Change-Id: I6234f0f60b9ed57b8b144159f3fe9c0b756df1e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70513 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70816 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Fixes FFDC for files moved to genericStephen Glancy2019-06-141-67/+0
| | | | | | | | | | | | | | | Change-Id: Ibd639646548cfe0745127419c151a67635e8ae75 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77343 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77420 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_npll_setup -- update SS enablement for p9aJoe McGill2019-06-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Axone has two spread PLLs that can individually synchronized, so the TOD timer facility grew two enable bits. Set both of them to synchronize both PLLs at the same time. The enable bits are don't care on Nimbus/Cumulus so the procedure will still work the same way there. Check only the status of one PLL, knowing that if both are enabled, either both or none will get started by the TOD. This maintains Nimbus/Cumulus compatibility on the checking part. Change-Id: Ife3a5164037362f1c392146bd7e27ef69bb1a0cd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78221 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78230 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9.filter.pll.scan.initfile -- update CP filter config for p9aJoe McGill2019-06-141-0/+17
| | | | | | | | | | | | | | | | | | CP refclock input is expected to be 100MHz for p9a Change-Id: I664dd9122f260fe1abb25c01c813ffadc289f460 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78117 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78120 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Added chip ec attribute for PCI cache injection.Ricardo Mata Jr2019-05-311-0/+7
| | | | | | | | | | | Change-Id: I39620763eb3f4d1f35cddba5cf5eee39a24fb13a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77764 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77774 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Set IOO clockgate_disable for Axone HW481539 / HW438727Ben Gass2019-05-311-3/+11
| | | | | | | | | | | | | | | | | | Axone defect HW481539. Using attribute for HW438727. Change-Id: Ifa23b2fc07b3a1b324f9815af26f38cd55d45a1b Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77984 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77996 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Update npu initfiles for AxoneBen Gass2019-05-311-0/+16
| | | | | | | | | | | | | | Change-Id: Ie33a3b4dc17f4c4ebd49b6799b9032a2b3aaab09 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77847 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: NICHOLAS J. OLLERICH <njolleri@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77888 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Fabric inits update for AxoneJenny Huynh2019-05-211-1/+18
| | | | | | | | | | | | | | | Change-Id: I7fd20b531154d7109b191f78c2400320552b611e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77544 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77555 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_chiplet_reset: Add missing OB3 clock muxes for AxoneJoachim Fenkes2019-05-161-2/+5
| | | | | | | | | | | | | Change-Id: Ied8f97e50aedad42d9a3b5f7d2156743b3f89dc1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77289 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77372 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Synch up OMI and MCA frequenciesDan Crowell2019-05-152-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an intrinsic link between ATTR_FREQ_MCA_MHZ and ATTR_FREQ_OMI_MHZ and ATTR_MC_PLL_BUCKET. -ATTR_MC_PLL_BUCKET will be read-only, platforms will return the value based on ATTR_FREQ_OMI_MHZ. -ATTR_FREQ_MCA_MHZ will be read-only (again), platforms will return the value based on ATTR_FREQ_OMI_MHZ. -ATTR_FREQ_OMI_MHZ will be writeable, defaulted by mrw/config file, written by mss_freq_system. -OMI_PLL_FREQ_LIST was be expanded to include the value of ATTR_FREQ_MCA_MHZ. Platforms will use ATTR_FREQ_OMI_MHZ (and VCO) as the key into OMI_PLL_FREQ_LIST to determine the value of ATTR_MC_PLL_BUCKET and ATTR_FREQ_MCA_MHZ Change-Id: I17681b8b1ff8ad6b195fc741e20e48ac60ce1c99 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76877 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Dev-Ready: Steven B. Janssen <janssens@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76903 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Fixed the ccs port merge conflicts and added lab codeMatthew Hickman2019-05-151-4/+4
| | | | | | | | | | | | | | | | Change-Id: I665ea2460a5ace289b17ae868b07a8876b65a0c8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75236 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76884 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: Handle PIB Reset with data check handler on all GPEsYue Du2019-05-156-8/+98
| | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I121aaf5efb579fde88829f2ef5354ad4c8b6d77b CQ:SW447494 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68622 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68629 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* VDM(Part 3): Image build changes for quad level VDMPrem Shanker Jha2019-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | Commit accomplishes following: - enables CME booting using new CPMR layout - copies new definition of poundw to LPSPB - enables quad level LPSPB - implements new CPMR layout that supports customized LPSPB. - for old VPD version, retains old CPMR layout Change-Id: I66a13579e0edbc046226db259a736416e1e5c268 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75272 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75276 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Axone Xbus LinearityChris Steffen2019-05-051-0/+19
| | | | | | | | | | | | | | | Change-Id: I7890146ba7e05197910bdbe77d19f221b7b5b912 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76460 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76470 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add p9a.omi.pll.scan.initfile and ifCompiler support.Ben Gass2019-05-051-1/+20
| | | | | | | | | | | | | | | | | | | | | | | Frequencies supported for OMI: OMI VCO Data rate MCA_FREQ 19200, 0, DDR4-2400 1200 21330, 0, DDR4-2667 1333 23460, 0, DDR4-2933 1466 23460, 1, DDR4-2933 1466 25600, 1, DDR4-3200 1600 Change-Id: Ideebc4636f79302f3728264fb8dc63a3ba4e807a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/54198 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/54201 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_tracearray: Updates for AxoneJoachim Fenkes2019-05-053-35/+59
| | | | | | | | | | | | | | | | | | | | | | | | Add new trace bus names and trace array definitions for Axone. Some trace buses are just renamed, but I decided to add separate constants for clarity. Simplify the "can I dump the core trace arrays?" logic since no chips of the P9 family can have their core traces dumped via SCOM. Improve SBE size of ta_defs. Change-Id: I276f867a7fe9387fec9b7b216137767154ba1928 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67593 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67599 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* p9_sbe_nest_enable_ridi: Open up PCIe refclk driversJoachim Fenkes2019-04-281-1/+2
| | | | | | | | | | | | | | | | | As a fix for an X-state issue on Axone (HW476237), we added a root control bit that will inhibit the PCIe refclk drivers. Once the PCIe chiplets are initialized, we can lift this inhibit. Change-Id: I22562b3bb3d75c3a0d67a271c49d5c0f22218c3d Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70376 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70385 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Move MCBIST lib to generic folderAlvin Wang2019-04-251-10/+0
| | | | | | | | | | | | | | | | Change-Id: Ib717742707bea6a626131578f5a3b1aeebc76281 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69677 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72029 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Add ATTR_FREQ_OMI_MHZLouis Stermole2019-04-181-0/+16
| | | | | | | | | | | | | | | Change-Id: I4f2cfad77821b39e635c7cee3e068ec7628f778a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76013 Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76096 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* PM: Fixed error path handling of getscoms in HWP p9_query_core_access_state.Prem Shanker Jha2019-04-161-86/+58
| | | | | | | | | | | | | | | | | | | | | | | | When is core is in STOP2 or greater, HWP will not be able to SCOM clock status register of core. Use of FAPI_TRY to scom such a register returns failure to caller. With thisi, caller fails to understand if output status variables are good or not. Commit modifies this behavior to always return SUCCESS and a core state which is consistent with known status of core. Key_Cronus_Test=PM_REGRESS Change-Id: I6365ff0e52c3eb77d9d8ac749f9649a81cdadcac CQ: SW460324 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75267 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75338 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Added code for exp_getecid and unit testsMark Pizzutillo2019-04-161-4/+8
| | | | | | | | | | | | | | Change-Id: Id0a8fcf7c28d67c1bcb4ba98ff7af6d94dfa6364 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74784 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75352 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
* Update p9_mss_eff_grouping for Axone supportBen Gass2019-04-025-14/+20
| | | | | | | | | | | | | | | | Add p9a_omi_setup_bars procedure Add eclipse project files to .gitignore Change-Id: Ia18cd213ac8b3682e5718b3c631dad631b97170f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67755 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67763 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
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