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* SBE move import`Shakeeb2016-09-0133-3149/+0
* HWP/LIB: add fencing to common poweronoff moduleYue Du2016-08-241-9/+0
* CORE/CACHE: istep4 functional fix collectionYue Du2016-08-171-0/+6
* scan HWP updatesJoe McGill2016-08-162-90/+22
* Update prologs of mirrored files to have apache licenseStephen Cprek2016-08-1533-248/+482
* p9_ring_id.h: move ring IDs to plain C header fileMartin Peschke2016-08-093-3/+3
* scan HWP updatesJoe McGill2016-08-013-38/+45
* CORE/CACHE: remove runinit procedures.Yue Du2016-07-263-125/+0
* Level 2 HWP for p9_hcd_cache_chiplet_l3_dcc_setupAnusha Reddy Rangareddygari2016-07-212-5/+33
* VBU IPL -- update sim PLL configurationJoe McGill2016-07-201-10/+1
* CORE/CACHE: fix initf procedures on ring IDs and ex partial goodYue Du2016-07-083-36/+49
* Cache/Core: Istep4 procedure changes for model 9038 and aboveYue Du2016-06-175-83/+142
* Update makefile for new procedures.Sachin Gupta2016-06-081-0/+2
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2016-06-082-0/+131
* Level 1 HWP for p9_hcd_cache_chiplet_l3_dcc_setupAnusha Reddy Rangareddygari2016-06-082-0/+101
* partial good/hang pulse updates to support all sim models/clock ratiosJoe McGill2016-06-081-0/+5
* p9.core.common.initfile -- clear PSSCR[RL] for cache contained modeJoe McGill2016-05-201-1/+1
* add core/cache initfilesJoe McGill2016-05-161-6/+66
* invoke cache SCOM initfilesJoe McGill2016-05-111-1/+40
* Single SEEPROM image for SBESachin Gupta2016-05-031-0/+1
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2016-04-2514-473/+523
* HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34Yue Du2016-02-2512-435/+468
* Makefile InfraSunil.Kumar2015-12-082-0/+60
* Avoid hash collision in ppe.Sachin Gupta2015-12-041-1/+1
* Fix for ppe compilatoin errorSunil.Kumar2015-11-201-25/+26
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2015-11-1920-626/+353
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2015-11-172-0/+115
* PPE-HWP: [Level 2] Poweronoff Hcode Procedures using APIDavid Young2015-11-172-138/+0
* PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute definedYue Du2015-11-172-0/+138
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2015-11-172-0/+274
* PPE-HWP: [Level 2] Dllsetup Hcode ProcedureDavid Young2015-11-172-333/+0
* PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute definedYue Du2015-11-172-0/+333
* PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute definedYue Du2015-11-0625-0/+2414
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