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talos-sbe
04-16-2019
07-25-2019
master
Blackbird™ SBE sources
Raptor Computing Systems
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path:
root
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import
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chips
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p9
/
procedures
/
hwp
/
cache
Commit message (
Expand
)
Author
Age
Files
Lines
*
SBE move import`
Shakeeb
2016-09-01
33
-3149
/
+0
*
HWP/LIB: add fencing to common poweronoff module
Yue Du
2016-08-24
1
-9
/
+0
*
CORE/CACHE: istep4 functional fix collection
Yue Du
2016-08-17
1
-0
/
+6
*
scan HWP updates
Joe McGill
2016-08-16
2
-90
/
+22
*
Update prologs of mirrored files to have apache license
Stephen Cprek
2016-08-15
33
-248
/
+482
*
p9_ring_id.h: move ring IDs to plain C header file
Martin Peschke
2016-08-09
3
-3
/
+3
*
scan HWP updates
Joe McGill
2016-08-01
3
-38
/
+45
*
CORE/CACHE: remove runinit procedures.
Yue Du
2016-07-26
3
-125
/
+0
*
Level 2 HWP for p9_hcd_cache_chiplet_l3_dcc_setup
Anusha Reddy Rangareddygari
2016-07-21
2
-5
/
+33
*
VBU IPL -- update sim PLL configuration
Joe McGill
2016-07-20
1
-10
/
+1
*
CORE/CACHE: fix initf procedures on ring IDs and ex partial good
Yue Du
2016-07-08
3
-36
/
+49
*
Cache/Core: Istep4 procedure changes for model 9038 and above
Yue Du
2016-06-17
5
-83
/
+142
*
Update makefile for new procedures.
Sachin Gupta
2016-06-08
1
-0
/
+2
*
HWP-CACHE/CORE:istep4 procedures updates
Yue Du
2016-06-08
2
-0
/
+131
*
Level 1 HWP for p9_hcd_cache_chiplet_l3_dcc_setup
Anusha Reddy Rangareddygari
2016-06-08
2
-0
/
+101
*
partial good/hang pulse updates to support all sim models/clock ratios
Joe McGill
2016-06-08
1
-0
/
+5
*
p9.core.common.initfile -- clear PSSCR[RL] for cache contained mode
Joe McGill
2016-05-20
1
-1
/
+1
*
add core/cache initfiles
Joe McGill
2016-05-16
1
-6
/
+66
*
invoke cache SCOM initfiles
Joe McGill
2016-05-11
1
-1
/
+40
*
Single SEEPROM image for SBE
Sachin Gupta
2016-05-03
1
-0
/
+1
*
HWP-CACHE/CORE:istep4 procedures updates
Yue Du
2016-04-25
14
-473
/
+523
*
HWP-CORE/CACHE: Update Istep 4 procedures regressed on model 34
Yue Du
2016-02-25
12
-435
/
+468
*
Makefile Infra
Sunil.Kumar
2015-12-08
2
-0
/
+60
*
Avoid hash collision in ppe.
Sachin Gupta
2015-12-04
1
-1
/
+1
*
Fix for ppe compilatoin error
Sunil.Kumar
2015-11-20
1
-25
/
+26
*
PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocks
Yue Du
2015-11-19
20
-626
/
+353
*
PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocks
Yue Du
2015-11-17
2
-0
/
+115
*
PPE-HWP: [Level 2] Poweronoff Hcode Procedures using API
David Young
2015-11-17
2
-138
/
+0
*
PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute defined
Yue Du
2015-11-17
2
-0
/
+138
*
PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocks
Yue Du
2015-11-17
2
-0
/
+274
*
PPE-HWP: [Level 2] Dllsetup Hcode Procedure
David Young
2015-11-17
2
-333
/
+0
*
PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute defined
Yue Du
2015-11-17
2
-0
/
+333
*
PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute defined
Yue Du
2015-11-06
25
-0
/
+2414