diff options
| author | Yue Du <daviddu@us.ibm.com> | 2015-04-15 15:48:34 -0500 |
|---|---|---|
| committer | Amit J. Tendolkar <amit.tendolkar@in.ibm.com> | 2015-11-06 04:07:11 -0600 |
| commit | 1848d0d30e689d1b7f3dcbdee301c405d5723888 (patch) | |
| tree | f6ab7c4c46130a2599fe9b5f176a4b5675ca210e /import/chips/p9/procedures/hwp/cache | |
| parent | 9112cd33efcb4f4575da4ef8cfa9699ed47258e9 (diff) | |
| download | talos-sbe-1848d0d30e689d1b7f3dcbdee301c405d5723888.tar.gz talos-sbe-1848d0d30e689d1b7f3dcbdee301c405d5723888.zip | |
PPE-HWP: [Level 1] Cache + Core Hcode Procedures with API and Attribute defined
Patch 6 Update:
FW owner email address fix
Patch 5 Update:
target types fixed, all compiles now.
(Will rework them when multicast target is ready in Fapi2)
add @brief to function doxygen
add FW Owners to all headers
typo fixes
Note: NOT fixed with this update or this level 1 release but was commented:
1) still need a solution for document attributes in doxygen headers.
2) All traces in procedures including entry/exit are going to be
finalized in future releases as the function body development
reaches next maturity. There will be more discussion
in-term/inter-term on how to do tracing overall on these procs,
dont want to block this release because of it.
Patch 3 Update:
addressed comments from Patch 2 review.
merged p9_hcd_cache/core_sp_runtime_scom and p9_hcd_cache/core_host_runtime_scom
into p9_hcd_cache/core_ras_runtime_scom based on changes in P9_IPL_Flow.doc(v55)
Patch 2 Update:
renamed proc_* to p9_* for all procedure filenames per comment in Patch 1
Note:
1) Due to ongoing interface discussion and resolution, some of these procedures
are not yet ready for building under Cronus. Regular Fapi2 build is ready.
If you see some of Fapi2 Target Types in these procedures are not in Fapi2 yet,
that is because they are currently in discussion of addition to Fapi2.
2) There are ongoing function body development in the code, which are all
"#if 0" out in this level 1 release. The effective code in all files are
only the API prototypes. Please focus your review only to the interfaces.
3) cache/core runinit is for SGPE and CME at runtime only, not for IPL or SBE.
4) common_pro_epi_log and common_poweronoff are subroutine support(not in IPL_Flow)
Change-Id: Ic8e10960edc14dd15b350d9e367f79c052cf555a
Original-Change-Id: I46f07bb3e7cf050256c123e7f16982ccead2ceda
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17193
Reviewed-by: Reshmi Nair <reshminair@in.ibm.com>
Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Tested-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21813
Tested-by: Jenkins Server
Reviewed-by: Amit J. Tendolkar <amit.tendolkar@in.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/cache')
25 files changed, 2414 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H new file mode 100644 index 00000000..dc2f1563 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H @@ -0,0 +1,48 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache.H +/// @brief Cache Chiplet Procedure Includes +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_H__ +#define __P9_HCD_CACHE_H__ + +#include <p9_hcd_cache_arrayinit.H> +#include <p9_hcd_cache_chiplet_init.H> +#include <p9_hcd_cache_chiplet_reset.H> +#include <p9_hcd_cache_dpll_setup.H> +#include <p9_hcd_cache_gptr_time_initf.H> +#include <p9_hcd_cache_initf.H> +#include <p9_hcd_cache_occ_runtime_scom.H> +#include <p9_hcd_cache_poweron.H> +#include <p9_hcd_cache_ras_runtime_scom.H> +#include <p9_hcd_cache_repair_initf.H> +#include <p9_hcd_cache_runinit.H> +#include <p9_hcd_cache_scomcust.H> +#include <p9_hcd_cache_scominit.H> +#include <p9_hcd_cache_startclocks.H> + +#endif // __P9_HCD_CACHE_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C new file mode 100644 index 00000000..df68ed33 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C @@ -0,0 +1,165 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.C +/// @brief EX Initialize arrays +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Use ABIST engine to zero out all arrays +/// Upon completion, scan0 flush all rings +/// except Vital, Repair, GPTR, TIME and DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_arrayinit.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Initialize Cache Arrays +//----------------------------------------------------------------------------- + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + uint32_t scan; + uint32_t loop; + + // Procedure Prereq : P0 is pointing to the targeted EX chiplet + // submodules: + // seeprom_array_init_module + // ex_scan0 + + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + *** Array Init and Scan0 Cleanup for EX Chiplets ***"); + + // SBE Address Base Register Setups + // Setup PRV_BASE_ADDR1; points to selected EX chiplet + // - mr P1, P0 + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Copy selected EX info from P0 to P1"); + + // Step 1: Array Init for selected EX chiplet + // ARRAY INIT module -> see p9_sbe_tp_array_init.S + // + // At entry: + // + // P1 : The chiplet ID/Multicast Group + // D1 : Clock Regions for Array Init + // + // At exit: + // + // P0, D0, D1, CTR : destroyed + // P1, A0, A1 : maintained + // + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Calling Array Init Subroutine"); + + // >>> IPL/Winkle + // \bug Need to exclude DPLL ring for IPL + // li D1, SCAN_ALLREGIONEXVITAL + // = li D1, SCAN_CLK_ALLEXDPLL + scan = SCAN_CLK_ALLEXDPLL; + + // Execute the array init + // = bsr seeprom_array_init_module + seeprom_array_init_module(scan); + + // Restore P0 with selected EX chiplet info + // - mr P0, P1 + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Copy selected EX info back from P1 to P0"); + + // Step 2: Scan0 for selected EX chiplet except PRV, GPTR, TIME and DPLL + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Calling Scan0 Subroutine"); + + // taken from p9_sbe_ex_chiplet_init + + // >>> IPL/Winkle scan flush - all except vital + + // Hook to bypass in Sim + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Init: Scan0 Module executed: \ + Scan all except vital, DPL, GPTR, and TIME scan chains"); + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + + // \bug remove DPLL ring + // ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALL + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL + // = .endr + for(loop = 0; loop < P9_SCAN0_FUNC_REPEAT; loop++) + { + ex_scan0(SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL); + } + + // - 1: + + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + *** End of Procedure ***"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H new file mode 100644 index 00000000..c031c31e --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H @@ -0,0 +1,56 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.H +/// @brief EX Initialize arrays +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_ARRAYINIT_H__ +#define __P9_HCD_CACHE_ARRAYINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_arrayinit_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_arrayinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief EX Initialize arrays +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_ARRAYINIT_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C new file mode 100644 index 00000000..1b50c094 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C @@ -0,0 +1,135 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.C +/// @brief EX Flush/Initialize +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Scan0 flush all configured chiplet rings except Vital, GPTR, TIME and DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_chiplet_init.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +//#define SIM_PLL +//#define SIM_SPEEDUP +////#define SCAN0_DISABLE +//#define STEP_CHIPLET_INIT_0 0x0 // Resetting DPLL +//#define STEP_CHIPLET_INIT_1 0x1 // Core+ECO glmux switch (IPL/Winkle) +//#define STEP_CHIPLET_INIT_2 0x2 // Core glmux switch (Sleep) +//#define STEP_CHIPLET_INIT_3 0x3 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_4 0x4 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_5 0x5 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_6 0x6 // Before Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_7 0x7 // After Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_8 0x8 // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_9 0x9 // After Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_A 0xA // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_B 0xB // After Core Func flush for Sleep +//#define PORE_REFCLK_CYCLES 1 // \todo need real value for hdw +//#define DPLL_LOCK_DELAY 8192*PORE_REFCLK_CYCLES + +//----------------------------------------------------------------------------- +// Procedure: EX Flush/Initialize +//----------------------------------------------------------------------------- + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + uint32_t loop; + + // Procedure Prereq: + // p9_sbe_ex_chiplet_reset, p9_sbe_ex_dpll_initf, p9_sbe_ex_pll_initf + + FAPI_INF("<p9_hcd_cache_chiplet_init>: Entering procedure"); + + // Look for PSCOM error on any chip, fail if we find one + // scan0 flush all configured chiplet rings except EX DPLL + // call ex_scan0_module( ) + + // >>> IPL/Winkle scan flush - all except vital + + // Hook to bypass in Sim + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Init: Scan0 Module executed: \ + Scan all except vital, DPL, GPTR, and TIME scan chains"); + // - updatestep STEP_CHIPLET_INIT_6, D0, P1 + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL + // = .endr + for(loop = 0; loop < P9_SCAN0_FUNC_REPEAT; loop++) + { + ex_scan0(SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL); + } + + // - updatestep STEP_CHIPLET_INIT_7, D0, P1 + // - 1: + + FAPI_INF("<p9_hcd_cache_chiplet_init>: Exiting procedure"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H new file mode 100644 index 00000000..45ad8b2f --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.H +/// @brief EX Flush/Initialize +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_CHIPLET_INIT_H__ +#define __P9_HCD_CACHE_CHIPLET_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_chiplet_init_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_init_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + + +/// @brief EX Flush/Initialize +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_CHIPLET_INIT_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C new file mode 100644 index 00000000..ec5a64c6 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -0,0 +1,307 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_reset.C +/// @brief Cache Chiplet Reset +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Reset quad chiplet logic +/// Scan0 flush entire cache chiplet +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_chiplet_reset.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +// GP3 Bits +// 1 - PCB_EP_RESET +// 2 - GLMMUX Reset +// 3 - PLL_TEST Enable +// 4 - PLLRST - PLL Reset +// 5 - PLL Bypass +// 11 - D_MODE for Vital +// 13 - MPW2 for Vital +// 14 - PMW1 for Vital +// 18 - FENCE_EN for chiplet +// 22 - Resonant Clock disable +// 23:24 - Glitchless Mux Sel +// 25: - ?? (set because System Pervasive flow does this) +// Background: system pervasive as the following setting in their tests: +// 7C1623C000000000 +// Bits set: +// 1, 2, 3, 4, 5, 11, 13, 14, 18, 22, 23, 24, 25 +//#define GP3_INIT_VECTOR (BITS(1,5)|BIT(11)|BIT(13)|BIT(14)|BIT(18)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) + +// hang counter inits +//#define HANG_P1_INIT 0x0400000000000000 +//#define PCB_SL_ERROR_REG_RESET 0xFFFFFFFFFFFFFFFF +//#define STEP_CHIPLET_RESET_1 0x1 // After start of vital clocks +//#define STEP_CHIPLET_RESET_2 0x2 // After fence drop +//#define STEP_CHIPLET_RESET_3 0x3 // Before GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_4 0x4 // After GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_5 0x5 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_6 0x6 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_7 0x7 // Before GPTR flush for Sleep +//#define STEP_CHIPLET_RESET_8 0x8 // After GPTR flush for Sleep + +//------------------------------------------------------------------------------ +// Procedure: Cache Chiplet Reset +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) + { + +#if 0 + uint32_t loop; + + ///////////////////////////////////////////////////////////////// + // repeat some init steps of chiplet_init + ///////////////////////////////////////////////////////////////// + + // If there is a unused, powered-off EX chiplet which needs to be + // configured in the following steps to setup the PCB endpoint. + + // Skip the PCB endpoint config steps for sleep so that fences don't + // get dropped (eg by dropping chiplet_enable (GP3(0)). + + FAPI_INF("<p9_hcd_cache_chiplet_reset>: \ + Repeat dedicated pervasive init steps for EX "); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Reset GP3 for EX chiplet, step needed for hotplug"); + // = sti GENERIC_GP3_0x000F0012,P0,GP3_INIT_VECTOR + FAPI_TRY(putScom(i_target, GENERIC_GP3_0x000F0012, + fapi2: buffer<uint64_t>(23452345))); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Drop aync reset to Glitchless Mux"); + // = sti GENERIC_GP3_AND_0x000F0013,P0,~BIT(2) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2: buffer<uint64_t>().flush<1>().clearBit<2>())); + + // 19:21 PM_PI_DECODE needs to be 010 for functional operation(set bit 20) + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Put DPLL in functional mode"); + // = sti GENERIC_GP3_OR_0x000F0014,P0, BIT(20) + FAPI_TRY(putScom(i_target, GENERIC_GP3_OR_0x000F0014, + fapi2::buffer<uint64_t>().setBit<20>())); + + // - updatestep STEP_CHIPLET_RESET_1, D0, P1 + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Release endpoint reset for PCB"); + // = sti GENERIC_GP3_AND_0x000F0013,P0,~BIT(1) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2: buffer<uint64_t>().flush<1>().clearBit<1>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Partial good setting"); + // = sti GENERIC_GP3_OR_0x000F0014,P0,BIT(0) + FAPI_TRY(putScom(i_target, GENERIC_GP3_OR_0x000F0014, + fapi2::buffer<uint64_t>().setBit<0>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + PCB slave error reg reset"); + // = sti MASTER_PCB_ERR_0x000F001F,P0,PCB_SL_ERROR_REG_RESET + FAPI_TRY(putScom(i_target, MASTER_PCB_ERR_0x000F001F, + fapi2: buffer<uint64_t>(643564))); + + FAPI_DBG("Use timer mode for DPLL lock when enabled"); + // = sti EX_PMGP0_OR_0x100F0102, P0, BIT(7) + FAPI_TRY(putScom(i_target, EX_PMGP0_OR_0x100F0102, + fapi2::buffer<uint64_t>().setBit<7>())); + + // Set the DPLL Timer value for waiting on DPLL HOLDs in 35:36 + // 00 = 1024 cycles <---- + // 01 = 512 cycles + // 10 = 256 cycles + // 11 = 128 cycles + FAPI_DBG("Set the timer value for waiting on DPLL THOLDs"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(35)|BIT(36)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2: buffer<uint64_t>().flush<1>().insertFromRight<35, 2>(0))); + + // Only perform the disablement of PCBS-PM for the IPL work-around when + // doing IPL (eg skip if winkle; this whole section is skipped for sleep) + // >>> IPL + // FAPI_DBG("Disable the PCBS-PM as part of winkle enablement"); + // = sti EX_PMGP0_OR_0x100F0102, P0, BIT(0) + FAPI_TRY(putScom(i_target, EX_PMGP0_OR_0x100F0102, + fapi2: buffer<uint64_t>().setBit<0>())); + + // The following is performed for both IPL/Winkle and Sleep + + // Note: These are executed for sleep as well as these fences will have + // already been dropped + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove pervasive ECO fence;"); + // ECO Fence in 22 + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(22)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2: buffer<uint64_t>().flush<1>().clearBit<22>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove winkle mode before scan0 on EX chiplets is executed"); + // PM Exit States: WINKLE_EXIT_DROP_ELEC_FENCE + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove logical pervasive/pcbs-pm fence"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(39)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2: buffer<uint64_t>().flush<1>().clearBit<39>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove PB Winkle Electrical Fence GP3(27)"); + // = sti EX_GP3_AND_0x100F0013,P0,~(BIT(27)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2: buffer<uint64_t>().flush<1>().clearBit<27>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Configuring chiplet hang counters") ; + // = sti EX_HANG_P1_0x100F0021,P0,HANG_P1_INIT + data = 34654; // HANG_P1_INIT + FAPI_TRY(putScom(i_target, EX_HANG_P1_0x100F0021, + fapi2: buffer<uint64_t>(34654))); + // - updatestep STEP_CHIPLET_RESET_2, D0, P1 + + ////////////////////////////////////////////////////////////// + // perform scan0 module for pervasive chiplet (GPTR_TIME_REPR) + ////////////////////////////////////////////////////////////// + + // >>> IPL/Winkle scan flush - core and EX + + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF01 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + // \todo WORKAROUND UNTIL LOGIC CHANGES + // Drop the core2cache and cache2core fences to allow for L2 scanning + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove pervasive ECO fence;"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(20) | BIT(21)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2: buffer<uint64_t>().flush<1>().insertFromRight<20, 2>(0))); + + FAPI_DBG("EX Reset: Scan0 Module executed: \ + Scan the GPTR/TIME/REP rings"); + // - updatestep STEP_CHIPLET_RESET_3, D0, P1 + + // = .rept P9_SCAN0_GPTR_REPEAT + // = ex_scan0 SCAN_GPTR_TIME_REP, SCAN_CLK_ALL + // = .endr + for(loop = 0; loop < P9_SCAN0_GPTR_REPEAT; loop++) + { + ex_scan0(SCAN_GPTR_TIME_REP, SCAN_CLK_ALL); + } + + // - updatestep STEP_CHIPLET_RESET_4, D0, P1 + + // - 1: + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Reset: Scan0 Module executed: \ + Scan the all but GPTR/TIME/REP rings"); + // - updatestep STEP_CHIPLET_RESET_5, D0, P1 + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporarily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_GPTRTIMEREP, SCAN_CLK_ALL + // = .endr + for(loop = 0; loop < P9_SCAN0_FUNC_REPEAT; loop++) + { + ex_scan0(SCAN_ALL_BUT_GPTRTIMEREP, SCAN_CLK_ALL); + } + + // - updatestep STEP_CHIPLET_RESET_6, D0, P1 + + // Ensure CC interrupts are disabled before starting clock domains and dpll + // But only do it for Murano-DD1.x! + // - lpcs P1, STBY_CHIPLET_0x00000000 + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, BITS(0, 32) + // - andi D0, D0, CFAM_CHIP_ID_CHIP_MAJOR_MASK + // - cmpibrane D0, 1f, CFAM_CHIP_ID_MURANO_1 + + // - mr A0, P0 + // - mr D1, ETR + // - ls P0, CHIPLET0 + // - ls CTR, MAX_CORES + // - bra end_core_loop + + // - begin_core_loop: + // Inspect presence of current ex chiplet + // - andi D0, D1, BIT(32) + // - braz D0, continue_core + // Disable CC interrupts. + // - ld D0, EX_SYNC_CONFIG_0x10030000, P0 + // - ori D0, D0, BIT(6) + // - std D0, EX_SYNC_CONFIG_0x10030000, P0 + + // - continue_core: + // - adds P0, P0, 1 //Increment ex chiplet + // - rols D1, D1, 1 //Shift ex chiplet mask left + + // - end_core_loop: + // - loop begin_core_loop + // - mr P0, A0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H new file mode 100644 index 00000000..64a9c686 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H @@ -0,0 +1,56 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_reset.H +/// @brief Cache Chiplet Reset +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_CHIPLET_RESET_H__ +#define __P9_HCD_CACHE_CHIPLET_RESET_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_chiplet_reset_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_reset_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief Cache Chiplet Reset +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_CHIPLET_RESET_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C new file mode 100644 index 00000000..c4d6ce68 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C @@ -0,0 +1,104 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.C +/// @brief Load GPTR and Time for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// to produce #G VPD contents +/// Check for the presence of core override GPTR ring from image +/// (this is new fvor P9) +/// if found, apply; if not, apply core GPTR from image +/// Check for the presence of core override TIME ring from image; +/// if found, apply; if not, apply core base TIME from image +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_gptr_time_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load GPTR and Time for EX non-core +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) + { + +#if 0 + + // Set EX scan ratio to 1:1 as EX is still at refclock + FAPI_INF("<p9_sbe_ex_gptr_time_initf> : Set EX scan ratio to 1:1 ..."); + // = sti EX_OPCG_CNTL0_0x10030002, P0, 0x0 + FAPI_TRY(fapi2::putScom(i_target, EX_OPCG_CNTL0_0x10030002, 0x0)); + + // scan ring content shared among all chiplets + FAPI_DBG("Scanning EX GPTR rings...") + // - load_ring ex_gptr_perv skipoverride=1 + // - load_ring ex_gptr_dpll skipoverride=1 + // - load_ring ex_gptr_l3 skipoverride=1 + // - load_ring ex_gptr_l3refr skipoverride=1 + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX TIME rings...") + // - load_ring_vec_ex ex_time_eco + + + // Set EX scan ratio back to 8:1 + FAPI_INF("<p9_sbe_ex_gptr_time_initf> : Set EX scan ratio to 8:1 ..."); + // Inputs: A1 and P0 and D0, destroys D0 & D1 + // - .pibmem_port (PORE_SPACE_PIBMEM & 0xf) + // - lpcs P1, PIBMEM0_0x00080000 + // - ld D0, ex_scan_ratio_override, P1 + // - bsr set_scan_ratio_d0 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H new file mode 100644 index 00000000..17f035da --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.H +/// @brief Load GPTR and Time for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_GPTR_TIME_INIT_H__ +#define __P9_HCD_CACHE_GPTR_TIME_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_gptr_time_initf_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_gptr_time_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief Load GPTR and Time for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_GPTR_TIME_RING - EX target, uint32 +/// pointer to RS4 content.<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_GPTR_TIME_INIT_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C new file mode 100644 index 00000000..413f982e --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.C +/// @brief EX (non-core) scan init +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// Check for the presence of cache FUNC override rings from image; +/// if found, apply; if not, apply cache base FUNC rings from image +/// Note: FASTINIT ring (eg CMSK ring) is setup at this point to limit the +/// stumps that participate in FUNC ring scanning (this is new for P9). +/// (TODO to make sure the image build support is in place) +/// Note: all caches that are in the Cache Multicast group will be +/// initialized to the same values via multicast scans +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: EX (non-core) scan init +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + // - load_ring ex_lbst_eco conditional_override=1 + // - load_ring ex_abfa_eco conditional_override=1 + // - load_ring ex_cmsk_eco conditional_override=1 + // - load_ring ex_func_perv conditional_override=1 + // - load_ring ex_func_l3 conditional_override=1 + // - load_ring ex_func_l3refr conditional_override=1 + + //Sim Speedup for L3 refresh cycles + // - load_ring ex_regf_l3 conditional_override=1 + // - load_ring ex_regf_l3refr conditional_override=1 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H new file mode 100644 index 00000000..dabaf65e --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.H +/// @brief EX (non-core) scan init +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_INITF_H__ +#define __P9_HCD_CACHE_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_initf_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief EX (non-core) scan init +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_L2_FUNC_RING - EX target, uint32 +/// @attritem ATTR_CACHE_L3_FUNC_RING - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_INITF_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C new file mode 100644 index 00000000..95fb1ac8 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C @@ -0,0 +1,87 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.C +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from OCC code that are put somewhere TBD +/// (TODO . revisit with OCC FW team) +/// OCC FW sets up value in the TBD SCOM section +/// This was not leverage in P8 with the demise of CPMs +/// Placeholder at this point +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_occ_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX OCC runtime SCOMS +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, occ_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + FAPI_INF("Launching OCC Runtime SCOM routine") + // - bsrd D0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H new file mode 100644 index 00000000..a83a9b37 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.H +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_occ_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_occ_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief EX OCC runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_OCC_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C new file mode 100644 index 00000000..842f9b90 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C @@ -0,0 +1,165 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.C +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates by FSP/Host(including HostServices and Hypervisors) +/// that are put on the cache image by STOP API calls +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (the SBE case), return +/// Else call the function at the pointer; pointer is filled in by +/// STOP image build +/// Powerbus (MCD) and L3 BAR settings +/// Runtime FIR mask updates from PRD +/// L2/L3 Repairs +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_ras_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX FSP/HOST runtime scoms +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, sp_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching SP Runtime SCOM routine") + // - bsrd D0 + // - 1: + // + + // Run the SCOM sequence if the SCOM procedure is defined. + // - la A0, host_runtime_scom + // - ld D1, 0, A0 + // - braz D1, 1f + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Disable the AISS to allow the override + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~(BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = ori D0, D0, (BIT(15)) + // = andi D0, D0, ~(BIT(21)) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + + // Branch to sub_slw_runtime_scom() + FAPI_INF("Launching Host Runtime SCOM routine") + // - bsrd D1 + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + + // - bra 2f + // - 1: + + // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - 2: + + // If using cv_multicast, we need to set the magic istep number here + // - la A0, p9_sbe_select_ex_control + // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX + // - braz D0, 3f + FAPI_DBG("Setting istep num to magic number because cv_multicast is set") + // - lpcs P1, MBOX_SBEVITAL_0x0005001C + // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) + // - 3: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H new file mode 100644 index 00000000..2d88c30a --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.H +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_ras_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_ras_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief EX FSP/Host runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_RAS_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C new file mode 100644 index 00000000..f4bb4541 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C @@ -0,0 +1,81 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.C +/// @brief Load Repair ring for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: Repair Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in /// MVPD, but SBE image is customized with rings for booting cores +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_repair_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load Repair ring for cache +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX REPAIR rings...") + // - load_ring_vec_ex ex_repr_eco + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H new file mode 100644 index 00000000..5cb2ed5a --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.H +/// @brief Load Repair ring for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_REPAIR_INITF_H__ +#define __P9_HCD_CACHE_REPAIR_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_repair_initf_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_repair_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief Load Repair ring for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_REPAIR_RING - EX target, uint32 +/// pointer to RS4 content, VPD #R Keyword content(RS4)<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_REPAIR_INITF_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.C new file mode 100644 index 00000000..666ea28f --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.C @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_runinit.C +/// @brief execute all cache init procedures +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_runinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_runinit( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + return fapi2::FAPI2_RC_SUCCESS; + +#if 0 + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; +#endif + + } // Procedure + + +} // extern C + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.H new file mode 100644 index 00000000..f9e18bb8 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_runinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_runinit.H +/// @brief execute all cache init procedures +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_RUNINIT_H__ +#define __P9_HCD_CACHE_RUNINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_runinit_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_runinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + + +/// @brief execute all cache init procedures +/// +/// @param [in] i_target TARGET_TYPE_PROC_CHIP target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_runinit( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_RUNINIT_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C new file mode 100644 index 00000000..25fb0b97 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C @@ -0,0 +1,87 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.C +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// If CME, request PCB Mux. +/// Poll for PCB Mux grant +/// Else (SBE) +/// Nop (as the CME is not running in bringing up the first Core) +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_scomcust.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: Core Chiplet PCB Arbitration +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + + fapi2::buffer<uint64_t> data; + + //Dynamically built (and installed) routine that is inserted by the .XIP + //Customization. process. (New for P9) + //(TODO: this part of the process is a placeholder at this point) + //Dynamically built pointer where a NULL is checked before execution + //If NULL (a potential early value); return + //Else call the function at the pointer; + //pointer is filled in by XIP Customization + //Customization items: + //Epsilon settings scan flush to super safe + //Customize Epsilon settings for system config + //LCO setup (chiplet specific) + //FW setups up based victim caches + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H new file mode 100644 index 00000000..e702b364 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H @@ -0,0 +1,56 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.H +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_SCOMCUST_H__ +#define __P9_HCD_CACHE_SCOMCUST_H__ +extern "C" +{ + +/// @typedef p9_hcd_cache_scomcust_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_scomcust_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief Core Chiplet PCB Arbitration +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_SCOMCUST_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C new file mode 100644 index 00000000..2c0a2968 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C @@ -0,0 +1,124 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.C +/// @brief Cache Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Apply any SCOM initialization to the cache +/// Stop L3 configuration mode +/// Configure Trace Stop on Xstop +/// DTS Initialization sequense +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_scominit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Cache Customization SCOMs +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + /////// + // NCU + /////// + + /////// + // L3 + /////// + + FAPI_DBG("Configuring L3 disable"); + // - l3_setup L3_SETUP_ACTION_DISABLE, L3_SETUP_UNIT_L3 + + /////// + // OHA + /////// + + FAPI_DBG("Enable OHA to accept idle operations \ + by removing idle state override"); + // - setp1_mcreadand D1 + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + + //FAPI_DBG("Read OHA_MODE value: 0x%16llx", io_pore.d0.read()); + // = andi D0, D0, ~BIT(6) + data.clearBit<6>(); + + //FAPI_DBG("Updated OHA_MODE value: 0x%16llx", io_pore.d0.read()); + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + + // set trace stop on checkstop + // Get the ECID to apply trace setup to only Murano DD2+ / Venice + // - lpcs P1, STBY_CHIPLET_0x00000000 + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, (CFAM_CHIP_ID_CHIP_MASK | CFAM_CHIP_ID_MAJOR_EC_MASK) + // - cmpibraeq D0, 1f, (CFAM_CHIP_ID_MURANO | CFAM_CHIP_ID_MAJOR_EC_1 ) + + FAPI_DBG("Configuring EX chiplet trace arrays \ + to stop on checkstop/recoverable errors") + // = sti GENERIC_DBG_MODE_REG_0x000107C0, P0, BIT(7) | BIT(8) + FAPI_TRY(putScom(i_target, GENERIC_DBG_MODE_REG_0x000107C0, + fapi2: buffer<uint64_t>().insertFromRight<7, 2>(0x3))); + + // = sti GENERIC_DBG_TRACE_REG2_0x000107CB, P0, BIT(17) + FAPI_TRY(putScom(i_target, GENERIC_DBG_TRACE_REG2_0x000107CB, + fapi2: buffer<uint64_t>().setBit<17>())); + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H new file mode 100644 index 00000000..802b1f84 --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.H +/// @brief Cache Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_SCOMINIT_H__ +#define __P9_HCD_CACHE_SCOMINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_scominit_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_scominit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief Cache Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_SCOMINIT_H__ diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C new file mode 100644 index 00000000..c95b138c --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -0,0 +1,269 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.C +/// @brief Quad Clock Start +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Set (to be sure they are set under all conditions) core logical fences +/// (new for P9) +/// Drop pervasive thold +/// Setup L3 EDRAM/LCO +/// Drop pervasive fence +/// Reset abst clock muxsel, sync muxsel +/// Set fabric node/chip ID from the nest version +/// Clear clock controller scan register before start +/// Start arrays + nsl regions +/// Start sl + refresh clock regions +/// Check for clocks started +/// If not, error +/// Clear force align +/// Clear flush mode +/// Drop the chiplet fence to allow PowerBus traffic +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_startclocks.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +#define STEP_EX_START_CLOCKS_NSL 0x1 +#define STEP_EX_START_CLOCKS_SL 0x2 +#define STEP_EX_START_CLOCKS_RUNNING 0x3 +#define STEP_EX_START_CLOCKS_SUCCESS 0x4 + + +//------------------------------------------------------------------------------ +// Procedure: Quad Clock Start +//------------------------------------------------------------------------------ + + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + FAPI_INF("<p9_hcd_cache_startclocks>: \ + P8 Start EX-Clocks started"); + + // Drop the Pervasive THOLD + // PM Exit States: WINKLE_EXIT_DROP_PERV_THOLD + // = sti EX_PMGP0_AND_0x100F0101,P0, ~(BIT(4)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2: buffer<uint64_t>().flush<1>().clearBit<4>())); + + FAPI_DBG("Enabling L3 EDRAM/LCO setup"); + // - l3_setup L3_SETUP_ACTION_ENABLE, L3_SETUP_UNIT_L3_EDRAM + + // Drop perv fence GP0.63 multicast scomreg write + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(63) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2: buffer<uint64_t>().flush<1>().clearBit<63>())); + + // Reset abstclk_muxsel, synclk_muxsel (io_clk_sel) + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BITS(0,2) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2: buffer<uint64_t>().flush<1>().insertFromRight<0, 2>(0x0))); + + // Set ABIST_MODE_DC for core chiplets (core recovery) + // = sti GENERIC_GP0_OR_0x00000005, P0, BIT(11)|BIT(13) + FAPI_TRY(putScom(i_target, GENERIC_GP0_OR_0x00000005, + fapi2: buffer<uint64_t>().setBit<11>().setBit<13>())); + + // set fabric node/chip ID values (read from nest chiplet) + // read from nest chiplet + // - lpcs P1, NEST_CHIPLET_0x02000000 + // - ldandi D0, NEST_GP0_0x02000000, P1, BITS(40, 6) + // = std D0, GENERIC_GP0_OR_0x00000005, P0 + //FAPI_TRY(putScom(i_target, GENERIC_GP0_OR_0x00000005, data)); + + // Write ClockControl, Scan Region Register, + // set all bits to zero prior clock start + // = sti GENERIC_CLK_SCANSEL_0x00030007, P0, 0x0000000000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_SCANSEL_0x00030007, 0x0)); + + // Write ClockControl, Clock Region Register, Clock Start command + // (arrays + nsl only, not refresh clock region) EX Chiplet + // = sti GENERIC_CLK_REGION_0x00030006, P0, 0x4FF0060000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_REGION_0x00030006, + fapi2: buffer<uint64_t>(0x4FF0060000000000))); + // - updatestep STEP_EX_START_CLOCKS_NSL, D0, P1 + + // Write ClockControl, Clock Region Register, Clock Start command + // (sl + refresh clock region) EX Chiplet + // = sti GENERIC_CLK_REGION_0x00030006, P0, 0x4FF00E0000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_REGION_0x00030006, + fapi2: buffer<uint64_t>(0x4FF00E0000000000))); + // - updatestep STEP_EX_START_CLOCKS_SL, D0, P1 + + // Read Clock Status Register (EX chiplet) + // check for bits 27:29 eq. zero, no tholds on + // 27 ROX CLOCK_STATUS_DPLL_FUNC_SL status of dpll_func_sl_thold + // 28 ROX CLOCK_STATUS_DPLL_FUNC_NSL status of dpll_func_nsl_thold + // output not used + // 29 ROX CLOCK_STATUS_DPLL_ARY_NSL status of dpll_ary_nsl_thold + // output not used + + // Needed to resolve SLW reading using a multicast group + // Get P1 setup for the chiplets to be targeted. + // - setp1_mcreadand D0 + + // = ld D0, GENERIC_CLK_STATUS_0x00030008, P1 + FAPI_TRY(getScom(i_target, GENERIC_CLK_STATUS_0x00030008, data)); + // - xori D0, D0, 0x00000003FFFFFFFF + // - branz D0, error_clock_start + + FAPI_DBG("<p9_hcd_cache_startclocks>: \ + EX clock running now"); + // - updatestep STEP_EX_START_CLOCKS_RUNNING, D0, P1 + + // Read the Global Checkstop FIR of dedicated EX chiplet + // - setp1_mcreador D0 + // = ld D0, GENERIC_XSTOP_0x00040000, P1 + FAPI_TRY(getScom(i_target, GENERIC_XSTOP_0x00040000, data)); + // - branz D0, error_checkstop_fir + + FAPI_DBG("<p9_hcd_cache_startclocks>: \ + All checkstop FIRs on initialized EX are zero"); + + // Clear force_align in all Chiplet GP0 + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(3) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2: buffer<uint64_t>().flush<1>().clearBit<3>())); + + // Clear flushmode_inhibit in Chiplet GP0 + // Can't do this on Murano & Venice DD1.x due to a logic bug in L3 HW250462 + // - lpcs P1, PCBMS_DEVICE_ID_0x000F000F + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, CFAM_CHIP_ID_MAJOR_EC_MASK + // - cmpibraeq D0, 1f, CFAM_CHIP_ID_MAJOR_EC_1 + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(2) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2: buffer<uint64_t>().flush<1>().clearBit<2>())); + // - 1: + + // Clear core2cache and cache2core fences. Necessary for Sleep, + // redundant (already clear) but not harmful for IPL/Winkle + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(20)|BIT(21)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2: buffer<uint64_t>().flush<1>().insertFromRight<20, 2>(0x0))); + + // Disable PM and DPLL override + FAPI_INF("<p9_hcd_cache_startclocks>: \ + Disable PM and DPLL override"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(0)|BIT(3)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2: buffer<uint64_t>().flush<1>().insertFromRight<0, 4>(0x6))); + + // PM Exit States: WINKLE_EXIT_WAIT_ON_OHA + // Drop fence GP3.18 to unfence the chiplet + // CMO-20130516: First clear the pbus purge request bit(14) from AISS + // - setp1_mcreador D0 + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + data.clearBit<1>(); + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~BIT(14) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + FAPI_TRY(getScom(i_target, EX_OHA_AISS_IO_REG_0x10020014, data)); + data.clearBit<14>(); + FAPI_TRY(putScom(i_target, EX_OHA_AISS_IO_REG_0x10020014, data)); + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + data.setBit<1>(); + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + // Now drop pb fence bit(18) + // = sti GENERIC_GP3_AND_0x000F0013,P0, ~BIT(18) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2: buffer<uint64_t>().flush<1>().clearBit<18>())); + + // Drop fence GP3.26 to allow PCB operations to the chiplet + // = sti GENERIC_GP3_AND_0x000F0013,P0, ~BIT(26) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2: buffer<uint64_t>().flush<1>().clearBit<26>())); + // - updatestep STEP_EX_START_CLOCKS_SUCCESS, D0, P1 + FAPI_INF("<p9_hcd_cache_startclocks>: \ + Exiting procedure successfully"); + + // - ifidle D0, 1f + //Not idle Check secure mode + // - ifbitclrscom D1, D1, OTPC_M_SECURITY_SWITCH_0x00010005, P1, 1, 1f + //Trusted boot is set, set core trusted boot. + // = sti EX_TRUSTED_BOOT_EN_0x10013C03, P0, BIT(0) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2: buffer<uint64_t>().flush<1>().clearBit<0>())); + // - 1: + +//------------------------------------------------------------------------------ +// ERROR -- Clocks failed to start +//------------------------------------------------------------------------------ + error_clock_start: + FAPI_ERR("<p9_hcd_cache_startclocks>: \ + Clock Start Error on EX detected"); + // - reqhalt RC_SBE_EX_STARTCLOCKS_CLOCKS_NOT_STARTED + +//------------------------------------------------------------------------------ +// ERROR -- Checkstop detected +//------------------------------------------------------------------------------ + error_checkstop_fir: + FAPI_ERR("<p9_hcd_cache_startclocks>: \ + Checkstop FIR on initialized EX is not zero, \ + VITAL register was updated"); + // - reqhalt RC_SBE_EX_STARTCLOCKS_CHIP_XSTOPPED + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + + + diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H new file mode 100644 index 00000000..ebfe4abd --- /dev/null +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.H +/// @brief Quad Clock Start +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CACHE_STARTCLOCKS_H__ +#define __P9_HCD_CACHE_STARTCLOCKS_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_startclocks_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_startclocks_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief Quad Clock Start +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_STARTCLOCKS_H__ |
