HWP-CACHE/CORE:istep4 procedures updates

Change-Id: I707a936f8124f997c338ce01db205b958716a8da
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21489
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Tested-by: PPE CI
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21491
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

14 files changed, 523 insertions, 473 deletions

diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
index 9a2628b8..93c59e21 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
@@ -24,7 +24,6 @@
 ///   Use ABIST engine to zero out all arrays
 ///   Upon completion, scan0 flush all rings
 ///     except Vital, Repair, GPTR, TIME and DPLL
-///
 
 // *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
@@ -36,6 +35,8 @@
 //-----------------------------------------------------------------------------
 // Includes
 //-----------------------------------------------------------------------------
+
+#include <p9_misc_scom_addresses.H>
 #include <p9_perv_sbe_cmn.H>
 #include <p9_hcd_common.H>
 #include "p9_hcd_cache_arrayinit.H"
@@ -43,14 +44,12 @@
 //-----------------------------------------------------------------------------
 // Constant Definitions
 //-----------------------------------------------------------------------------
+
 enum P9_HCD_CACHE_ARRAYINIT_Private_Constants
 {
     LOOP_COUNTER = 0x0000000000042FFF,
-    REGIONS_EXCEPT_VITAL = 0x7FF,
-    REGIONS_FOR_PERV = 0x400,
-    SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCF,
-    SELECT_EDRAM = 0x0,
     SELECT_SRAM = 0x1,
+    SELECT_EDRAM = 0x0,
     START_ABIST_MATCH_VALUE = 0x0000000F00000000
 };
 
@@ -62,17 +61,44 @@ fapi2::ReturnCode
 p9_hcd_cache_arrayinit(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
-
     FAPI_INF(">>p9_hcd_cache_arrayinit");
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint16_t                                    l_region_array;
+    uint16_t                                    l_region_scan0;
+    uint8_t                                     l_attr_chip_unit_pos = 0;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV>      l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
 
-#ifndef P9_HCD_STOP_SKIP_ARRAYINIT
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET;
 
-    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
-        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_data64));
+    FAPI_DBG("Working on cache[%d] good EXs in QCSR[%016llX]",
+             l_attr_chip_unit_pos, l_data64);
+
+    l_region_array = p9hcd::SCAN0_REGION_ALL_BUT_EX_DPLL;
+    l_region_scan0 = p9hcd::SCAN0_REGION_ALL_BUT_EX_ANEP_DPLL;
+
+    if (l_data64 & BIT64(l_attr_chip_unit_pos << 1))
+    {
+        l_region_array |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR;
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR;
+    }
 
-    FAPI_DBG("Arrayinit all regions except Vital");
+    if (l_data64 & BIT64((l_attr_chip_unit_pos << 1) + 1))
+    {
+        l_region_array |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR;
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR;
+    }
+
+#ifndef P9_HCD_STOP_SKIP_ARRAYINIT
+
+    FAPI_DBG("Arrayinit all regions except vital/DPLL");
     FAPI_TRY(p9_perv_sbe_cmn_array_init_module(l_perv,
-             REGIONS_EXCEPT_VITAL,
+             l_region_array,
              LOOP_COUNTER,
              SELECT_SRAM,
              SELECT_EDRAM,
@@ -88,26 +114,19 @@ p9_hcd_cache_arrayinit(
     // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
     // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
     // all stumps less than 8191, the loop can be removed.
-    FAPI_DBG("Scan0 all except Vital/ANEP/DPLL, GPTR/REPR/TIME scan chains");
+
+    FAPI_DBG("Scan0 region:all_but_anep_dpll type:all_but_gptr_repr_time rings");
 
     for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
         FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
-                                              p9hcd::SCAN0_REGION_ALL_BUT_ANEP_PLL,
+                                              l_region_scan0,
                                               p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
 
 #endif
 
-#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT)
 fapi_try_exit:
-#endif
 
     FAPI_INF("<<p9_hcd_cache_arrayinit");
-
     return fapi2::current_err;
-
 }
 
-
-
-
-
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C
index d6de25fb..c7663876 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C
@@ -22,7 +22,6 @@
 ///
 /// Procedure Summary:
 ///   Scan0 flush all configured chiplet rings except Vital, GPTR, TIME and DPLL
-///
 
 // *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
@@ -53,32 +52,31 @@ p9_hcd_cache_chiplet_init(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
     FAPI_INF(">>p9_hcd_cache_chiplet_init");
+    /*
+    #ifndef P9_HCD_STOP_SKIP_FLUSH
 
-#ifndef P9_HCD_STOP_SKIP_FLUSH
-
-    //--------------------------------------------
-    // perform scan0 module for pervasive chiplet
-    //--------------------------------------------
-    // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
-    // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
-    // all stumps less than 8191, the loop can be removed.
-    uint32_t l_loop;
-    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
-        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+        //--------------------------------------------
+        // perform scan0 module for pervasive chiplet
+        //--------------------------------------------
+        // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+        // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+        // all stumps less than 8191, the loop can be removed.
 
-    FAPI_DBG("Scan0 all except Vital/DPLL, GPTR/TIME/REPR scan chains");
+        fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
+            i_target.getParent<fapi2::TARGET_TYPE_PERV>();
 
-    for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
-        FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
-                                              p9hcd::SCAN0_REGION_ALL_BUT_PLL,
-                                              p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
+        FAPI_DBG("Scan0 region:all_but_anep_dpll type:all_but_gptr_repr_time rings");
 
-fapi_try_exit:
+        for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                                  p9hcd::SCAN0_REGION_ALL_BUT_ANEP_DPLL,
+                                                  p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
 
-#endif
+    fapi_try_exit:
 
+    #endif
+    */
     FAPI_INF("<<p9_hcd_cache_chiplet_init");
-
     return fapi2::current_err;
 }
 
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
index 483001be..22e51aad 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
@@ -28,7 +28,6 @@
 ///      (attribute dependency Nimbus/Cumulus)
 ///    - Drop glsmux async reset
 ///   Scan0 flush entire cache chiplet
-///
 
 // *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
@@ -41,6 +40,7 @@
 // Includes
 //------------------------------------------------------------------------------
 
+#include <p9_misc_scom_addresses.H>
 #include <p9_quad_scom_addresses.H>
 #include <p9_perv_sbe_cmn.H>
 #include <p9_hcd_common.H>
@@ -54,84 +54,144 @@
 // Procedure: Cache Chiplet Reset
 //------------------------------------------------------------------------------
 
-
 fapi2::ReturnCode
 p9_hcd_cache_chiplet_reset(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
     FAPI_INF(">>p9_hcd_cache_chiplet_reset");
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint16_t                                    l_region_scan0;
+    uint64_t                                    l_l2gmux_input       = 0;
+    uint64_t                                    l_l2gmux_reset       = 0;
+    uint8_t                                     l_attr_chip_unit_pos = 0;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV>      l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    auto l_core_functional_vector =
+        i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+        (fapi2::TARGET_STATE_FUNCTIONAL);
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET;
+
+    FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_data64));
+    FAPI_DBG("Working on cache[%d], good EXs in QCSR[%016llX]",
+             l_attr_chip_unit_pos, l_data64);
+
+    l_region_scan0 = p9hcd::SCAN0_REGION_ALL_BUT_EX;
+
+    if (l_data64 & BIT64(l_attr_chip_unit_pos << 1))
+    {
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR;
+        l_l2gmux_reset |= BIT64(32);
+        l_l2gmux_input |= BIT64(34);
+    }
+
+    if (l_data64 & BIT64((l_attr_chip_unit_pos << 1) + 1))
+    {
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR;
+        l_l2gmux_reset |= BIT64(33);
+        l_l2gmux_input |= BIT64(35);
+    }
 
     //--------------------------
-    // Reset quad chiplet logic
+    // Reset cache chiplet logic
     //--------------------------
     // If there is an unused, powered-off cache chiplet which needs to be
     // configured in the following steps to setup the PCB endpoint.
 
-    FAPI_DBG("Init NET_CTRL0[0,1,3,4,5,12,13,14,18], step needed for hotplug");
-    fapi2::buffer<uint64_t> l_data64 = p9hcd::NET_CTRL0_INIT_VECTOR;
+    for(auto it : l_core_functional_vector)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                               it.getParent<fapi2::TARGET_TYPE_PERV>(),
+                               l_attr_chip_unit_pos));
+        FAPI_DBG("Assert core[%d] DCC reset via NET_CTRL0[2]",
+                 (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET));
+        FAPI_TRY(putScom(l_chip, (C_NET_CTRL0_WOR + (0x1000000 *
+                                  (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET))),
+                         MASK_SET(2)));
+    }
+
+    FAPI_DBG("Init NET_CTRL0[1-5,11-14,18,22,26],step needed for hotplug");
+    l_data64 = p9hcd::Q_NET_CTRL0_INIT_VECTOR;
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0, l_data64));
 
-    FAPI_DBG("Assert Progdly+DCC Bypass,L2 DCC Reset via NET_CTRL1[1,2,23,24]");
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WOR, MASK_OR(1, 2, 3)));
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WOR, MASK_OR(23, 2, 3)));
+    FAPI_DBG("Assert progdly/DCC bypass,L2 DCC reset via NET_CTRL1[1,2,23,24]");
+    l_data64.flush<0>().insertFromRight<1, 2>(0x3).insertFromRight<23, 2>(0x3);
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WOR, l_data64));
 
-    FAPI_DBG("Assert Skew Adjust Reset via NET_CTRL0[2]");
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(2)));
+    FAPI_DBG("Flip cache glsmux to DPLL input via PPM_CGCR[3]");
+    FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_OR(0, 4, 0x9)));
 
-    FAPI_DBG("Set DPLL ff_bypass to 1 via QPPM_DPLL_CTRL[2]");
+    FAPI_DBG("Flip L2 glsmux to DPLL input via QPPM_EXCGCR[34:35]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, l_l2gmux_input));
+
+    FAPI_DBG("Assert DPLL ff_bypass via QPPM_DPLL_CTRL[2]");
     FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, MASK_SET(2)));
 
-    FAPI_DBG("Drop Vital Thold via NET_CTRL0[16]");
+    FAPI_DBG("Drop vital thold via NET_CTRL0[16]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(16)));
 
-    FAPI_DBG("Init L3 glsmux reset/select via CLOCK_GRID_CTRL[0:3]");
-    FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_OR(0, 4, 0)));
+    FAPI_DBG("Drop cache glsmux reset via PPM_CGCR[0]");
+    FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(3)));
+
+    FAPI_DBG("Drop L2 glsmux reset via QPPM_EXCGCR[32:33]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_CLEAR, l_l2gmux_reset));
 
-    FAPI_DBG("Init L2 glsmux reset/select via EXCLK_GRID_CTRL[32:35]");
-    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_CLEAR, MASK_CLR(32, 4, 0xF)));
+    FAPI_DBG("Assert chiplet enable via NET_CTRL0[0]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(0)));
 
-    FAPI_DBG("Clear PCB Endpoint Reset via NET_CTRL0[1]");
+    FAPI_DBG("Drop PCB endpoint reset via NET_CTRL0[1]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(1)));
 
-    FAPI_DBG("Remove chiplet electrical fence via NET_CTRL0[26]");
+    FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(26)));
 
-    FAPI_DBG("Remove PCB fence via NET_CTRL0[25]");
+    FAPI_DBG("Drop PCB fence via NET_CTRL0[25]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25)));
 
+    FAPI_DBG("Set scan ratio to 1:1 in bypass mode via OPCG_ALIGN[47-51]");
+    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<47, 5>(0x0);
+    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
+
 #ifndef P9_HCD_STOP_SKIP_FLUSH
+    //--------------------------------------------
+    // perform scan0 module for pervasive chiplet
+    //--------------------------------------------
+    // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+    // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+    // all stumps less than 8191, the loop can be removed.
+
     // Putting in block to avoid c++ crosses initialization compile error
     {
-        //--------------------------------------------
-        // Perform scan0 module for pervasive chiplet
-        //--------------------------------------------
-        //Each scan0 will rotate the ring 8191 latches (2**13-1) and the longest
-        //ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
-        //all stumps less than 8191, the repeat can be removed.
         uint32_t l_loop;
-        fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
-            i_target.getParent<fapi2::TARGET_TYPE_PERV>();
 
-        FAPI_DBG("Scan0 the GPTR/TIME/REPR rings");
+        FAPI_DBG("Scan0 region:all_but_vital type:gptr_repr_time rings");
 
         for(l_loop = 0; l_loop < P9_HCD_SCAN_GPTR_REPEAT; l_loop++)
             FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
-                                                  p9hcd::SCAN0_REGION_ALL,
+                                                  l_region_scan0,
                                                   p9hcd::SCAN0_TYPE_GPTR_REPR_TIME));
 
-        FAPI_DBG("Scan0 all but the GPTR/TIME/REPR rings");
+        FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings");
 
         for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
             FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
-                                                  p9hcd::SCAN0_REGION_ALL,
+                                                  l_region_scan0,
                                                   p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
     }
 #endif
 
+    /// @todo scan_with_setpulse_module(L3 DCC)
+    ///FAPI_DBG("Drop L3 DCC bypass via NET_CTRL1[1]");
+    ///FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WAND, MASK_UNSET(1)));
+
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_cache_chiplet_reset");
-
     return fapi2::current_err;
 }
 
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
index 133da10b..7234ee0d 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
@@ -87,97 +87,46 @@ fapi2::ReturnCode
 p9_hcd_cache_dpll_setup(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
-    fapi2::buffer<uint64_t> l_data64;
-    uint32_t                l_timeout;
-
     FAPI_INF(">>p9_hcd_cache_dpll_setup");
+    fapi2::buffer<uint64_t>                  l_data64;
+    uint32_t                                 l_timeout;
 
-    // --------------
-    // DPLL SCAN
-    // --------------
-    FAPI_DBG("Set scan ratio to 1:1 in bypass mode");
-    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
-    l_data64.insertFromRight<47, 5>(0x0);
-    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
-
-#ifndef P9_HCD_STOP_SKIP_FLUSH
-    // Putting in block to avoid c++ crosses initialization compile error
-    {
-        //--------------------------------------------
-        // Perform scan0 module for pervasive chiplet
-        //--------------------------------------------
-        //Each scan0 will rotate the ring 8191 latches (2**13-1) and the longest
-        //ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
-        //all stumps less than 8191, the repeat can be removed.
-        uint32_t l_loop;
-        fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
-            i_target.getParent<fapi2::TARGET_TYPE_PERV>();
-
-        FAPI_DBG("Scan0 the DPLL/ANEP rings(GPTR type)");
-
-        for(l_loop = 0; l_loop < P9_HCD_SCAN_GPTR_REPEAT; l_loop++)
-            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
-                                                  p9hcd::SCAN0_REGION_DPLL_ANEP,
-                                                  p9hcd::SCAN0_TYPE_GPTR));
-
-        FAPI_DBG("Scan0 all DPLL/ANEP rings(func type)");
-
-        for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
-            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
-                                                  p9hcd::SCAN0_REGION_DPLL_ANEP,
-                                                  p9hcd::SCAN0_TYPE_FUNC));
-    }
-#endif
-
-#ifndef P9_HCD_STOP_SKIP_SCAN
-
-    /// @todo putRing(DPLL,FUNC) here
-
-#endif
-
-    FAPI_DBG("Set scan ratio to 8:1 in bypass mode");
-    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
-    l_data64.insertFromRight<49, 3>(0x7);
-    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
-
-    // --------------
-    // DPLL SETUP
-    // --------------
+    //----------------------------
+    // Prepare to start DPLL clock
+    //----------------------------
 
-    FAPI_DBG("Ensure DPLL in Mode 1, and set slew rate to a modest value");
+    FAPI_DBG("Assert DPLL in mode 1,set slew rate via QPPM_DPLL_CTRL[2,6-15]");
     l_data64.flush<0>().setBit<2>().insertFromRight<6, 10>(0x40);
     FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, l_data64));
 
-    FAPI_DBG("Drop DPLL Test Mode and Reset");
+    FAPI_DBG("Drop DPLL test mode and reset via NET_CTRL0[3,4]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_AND(3, 2, 0)));
 
-    FAPI_DBG("Drop DPLL Clock Region Fence");
+    FAPI_DBG("Drop DPLL clock region fence via NET_CTRL1[14]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(14)));
 
     // ----------------
     // Start DPLL clock
     // ----------------
 
-    FAPI_DBG("Set all bits to zero prior clock start via SCAN_REGION_TYPE");
+    FAPI_DBG("Clear all bits prior start DPLL clock via SCAN_REGION_TYPE");
     FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
 
-    FAPI_DBG("Start clock(arrays+nsl clock region) via CLK_REGION");
+    FAPI_DBG("Start DPLL clock(arrays+nsl clock region) via CLK_REGION");
     l_data64 = p9hcd::CLK_START_REGION_DPLL_THOLD_NSL_ARY;
     FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
 
     /// @todo parameterize delay
     FAPI_TRY(fapi2::delay(0, 1000000));
 
-    FAPI_DBG("Start clock(sl+refresh clock region) via CLK_REGION");
+    FAPI_DBG("Start DPLL clock(sl+refresh clock region) via CLK_REGION");
     l_data64 = p9hcd::CLK_START_REGION_DPLL_THOLD_ALL;
     FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
 
-    FAPI_DBG("Poll for DPLL clock running");
+    FAPI_DBG("Poll for DPLL clock running via CLOCK_STAT_SL[14]");
     l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
                 CACHE_DPLL_CLK_START_TIMEOUT_IN_MS;
 
-    // Read Clock Status Register (Cache chiplet)
-    // check for bits 4:14 eq. zero, no tholds on
     do
     {
         FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
@@ -191,85 +140,87 @@ p9_hcd_cache_dpll_setup(
 
     // This is necessary to ensure that the DPLL is in Mode 1(ff_bypass = 1)
     // If not, the lock times will go from ~30us to 3-5ms
-    /// @todo Determine whether or not we should POLL instead of put delay here.
-    FAPI_DBG("Wait for DPLL to lock");
+    FAPI_DBG("Poll for DPLL to lock via QPPM_DPLL_STAT");
     l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
                 CACHE_DPLL_LOCK_TIMEOUT_IN_MS;
 
     do
     {
         FAPI_TRY(getScom(i_target, EQ_QPPM_DPLL_STAT, l_data64));
-        break; /// @todo Skipping the lock checking until model is ready
+        ///@todo disable poll for DPLL lock until model setting in place
+        break;
     }
     while ((l_data64.getBit<63>() != 1 ) && (--l_timeout != 0));
 
     FAPI_ASSERT((l_timeout != 0),
                 fapi2::PMPROC_DPLL_LOCK_TIMEOUT()
                 .set_EQQPPMDPLLSTAT(l_data64),
-                "DPLL lock timeout");
-    FAPI_DBG("DPLL is locked");
+                "DPLL Lock Timeout");
+    FAPI_DBG("DPLL is locked now");
+
+    //--------------------------
+    // Cleaning up
+    //--------------------------
 
-    FAPI_DBG("Take DPLL out of bypass");
+    FAPI_DBG("Drop DPLL bypass via NET_CTRL0[5]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(5)));
 
-    FAPI_DBG("Switch L3 glsmux select to DPLL output");
-    FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(3)));
+    FAPI_DBG("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2)));
 
-    FAPI_DBG("Switch L2 glsmux select to DPLL output");
-    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, MASK_OR(34, 2, 3)));
+    FAPI_DBG("Set scan ratio to 4:1 in non-bypass mode via OPCG_ALIGN[47-51]");
+    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<47, 5>(0x3);
+    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
+
+    FAPI_DBG("Drop ANEP clock region fence via CPLT_CTRL1[10]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(10)));
+
+    FAPI_DBG("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(22)));
+
+    // ----------------
+    // Start ANEP clock
+    /// @todo remove this step starting with Chip Drop DT1
+    // ----------------
+
+    FAPI_DBG("Clear all bits prior start ANEP clock via SCAN_REGION_TYPE");
+    FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
+
+    FAPI_DBG("Start ANEP clock(arrays+nsl clock region) via CLK_REGION");
+    l_data64 = p9hcd::CLK_START_REGION_ANEP_THOLD_NSL_ARY;
+    FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
+
+    /// @todo parameterize delay
+    FAPI_TRY(fapi2::delay(0, 1000000));
+
+    FAPI_DBG("Start ANEP clock(sl+refresh clock region) via CLK_REGION");
+    l_data64 = p9hcd::CLK_START_REGION_ANEP_THOLD_ALL;
+    FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
+
+    FAPI_DBG("Poll for ANEP clock running via CLOCK_STAT_SL[10]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CACHE_ANEP_CLK_START_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
+    }
+    while(((l_data64 & BIT64(10)) != 0) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_ANEPCLKSTART_TIMEOUT().set_EQCLKSTAT(l_data64),
+                "ANEP Clock Start Timeout");
+    FAPI_DBG("ANEP clock running now");
+
+    FAPI_DBG("Drop skew adjust reset via NET_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(2)));
 
-    FAPI_DBG("Drop ff_bypass to switch into slew-controlled mode")
-    FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2)));
-    /*
-        FAPI_DBG("Drop ANEP Clock Region Fence");
-        FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(10)));
-
-        // ----------------
-        // Start ANEP clock
-        // ----------------
-
-        FAPI_DBG("Set all bits to zero prior clock start via SCAN_REGION_TYPE");
-        FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
-
-        FAPI_DBG("Start clock(arrays+nsl clock region) via CLK_REGION");
-        l_data64 = p9hcd::CLK_START_REGION_ANEP_THOLD_NSL_ARY;
-        FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
-
-        /// @todo parameterize delay
-        FAPI_TRY(fapi2::delay(0, 1000000));
-
-        FAPI_DBG("Start clock(sl+refresh clock region) via CLK_REGION");
-        l_data64 = p9hcd::CLK_START_REGION_ANEP_THOLD_ALL;
-        FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
-
-        FAPI_DBG("Poll for ANEP clock running");
-        l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
-                    CACHE_ANEP_CLK_START_TIMEOUT_IN_MS;
-
-        // Read Clock Status Register (Cache chiplet)
-        // check for bits 4:14 eq. zero, no tholds on
-        do
-        {
-            FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
-        }
-        while(((l_data64 & BIT64(10)) != 0) && ((--l_timeout) != 0));
-
-        FAPI_ASSERT((l_timeout != 0),
-                    fapi2::PMPROC_ANEPCLKSTART_TIMEOUT().set_EQCLKSTAT(l_data64),
-                    "ANEP Clock Start Timeout");
-        FAPI_DBG("ANEP clock running now");
-
-        // @todo is this bit really skew adjust? note it is set in chiplet reset
-        FAPI_DBG("Release skew adjust reset");
-        FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(2)));
-    */
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_cache_dpll_setup");
-
     return fapi2::current_err;
-
-} // Procedure
+}
 
 
 
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H
index ec7f682c..d99411f4 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H
@@ -20,13 +20,13 @@
 /// @file  p9_hcd_cache_dpll_setup.H
 /// @brief Quad DPLL Setup
 ///
-/// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
-/// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
-/// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team               : PM
-/// *HWP Consumed by        : SBE:SGPE
-/// *HWP Level              : 2
-///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
 
 #ifndef __P9_HCD_CACHE_DPLL_SETUP_H__
 #define __P9_HCD_CACHE_DPLL_SETUP_H__
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
index c4d6ce68..35d9c364 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -20,12 +20,6 @@
 /// @file  p9_hcd_cache_gptr_time_initf.C
 /// @brief Load GPTR and Time for EX non-core
 ///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
 /// Procedure Summary:
 ///   Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
 ///     to produce #G VPD contents
@@ -34,14 +28,18 @@
 ///   if found, apply;  if not, apply core GPTR from image
 ///     Check for the presence of core override TIME ring from image;
 ///   if found, apply;  if not, apply core base TIME from image
-///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
 
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
-#include <fapi2.H>
-//#include <common_scom_addresses.H>
-//will be replaced with real scom address header file
+
 #include "p9_hcd_cache_gptr_time_initf.H"
 
 //------------------------------------------------------------------------------
@@ -52,53 +50,59 @@
 // Procedure: Load GPTR and Time for EX non-core
 //------------------------------------------------------------------------------
 
-extern "C"
+fapi2::ReturnCode
+p9_hcd_cache_gptr_time_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
+    FAPI_INF(">>p9_hcd_cache_gptr_time_initf");
 
-    fapi2::ReturnCode
-    p9_hcd_cache_gptr_time_initf(
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
-    {
+#ifndef P9_HCD_STOP_SKIP_SCAN
 
-#if 0
+    FAPI_DBG("Scanning Cache GPTR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EQ_GPTR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        // Set EX scan ratio to 1:1 as EX is still at refclock
-        FAPI_INF("<p9_sbe_ex_gptr_time_initf> : Set EX scan ratio to 1:1 ...");
-        // = sti     EX_OPCG_CNTL0_0x10030002, P0, 0x0
-        FAPI_TRY(fapi2::putScom(i_target, EX_OPCG_CNTL0_0x10030002, 0x0));
+    FAPI_DBG("Scanning EX L3 GPTR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_GPTR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        // scan ring content shared among all chiplets
-        FAPI_DBG("Scanning EX GPTR rings...")
-        // - load_ring ex_gptr_perv skipoverride=1
-        // - load_ring ex_gptr_dpll skipoverride=1
-        // - load_ring ex_gptr_l3 skipoverride=1
-        // - load_ring ex_gptr_l3refr skipoverride=1
+    FAPI_DBG("Scanning EX L2 GPTR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L2_GPTR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        // scan chiplet specific ring content
-        FAPI_DBG("Scanning EX TIME rings...")
-        // - load_ring_vec_ex ex_time_eco
+    FAPI_DBG("Scanning EX L3 Refresh GPTR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_REFR_GPTR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
+    FAPI_DBG("Scanning Cache Analog GPTR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EQ_ANA_GPTR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        // Set EX scan ratio back to 8:1
-        FAPI_INF("<p9_sbe_ex_gptr_time_initf> : Set EX scan ratio to 8:1 ...");
-        // Inputs: A1 and P0 and D0, destroys D0 & D1
-        // -   .pibmem_port (PORE_SPACE_PIBMEM & 0xf)
-        // -    lpcs    P1, PIBMEM0_0x00080000
-        // -    ld      D0, ex_scan_ratio_override, P1
-        // -    bsr     set_scan_ratio_d0
+    FAPI_DBG("Scanning Cache DPLL GPTR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EQ_DPLL_GPTR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        return fapi2::FAPI2_RC_SUCCESS;
+    FAPI_DBG("Scanning Cache TIME Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EQ_TIME,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        FAPI_CLEANUP();
-        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+    FAPI_DBG("Scanning EX L3 TIME Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_TIME,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-#endif
-
-        return fapi2::FAPI2_RC_SUCCESS;
+    FAPI_DBG("Scanning EX L2 TIME Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L2_TIME,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-    } // Procedure
+    FAPI_DBG("Scanning EX L3 Reference TIME Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_REFR_TIME,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
+fapi_try_exit:
 
-} // extern C
+#endif
 
+    FAPI_INF("<<p9_hcd_cache_gptr_time_initf");
+    return fapi2::current_err;
+}
 
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H
index 17f035da..7ab147a0 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -20,23 +20,26 @@
 /// @file  p9_hcd_cache_gptr_time_initf.H
 /// @brief Load GPTR and Time for EX non-core
 ///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
 
 #ifndef __P9_HCD_CACHE_GPTR_TIME_INIT_H__
 #define __P9_HCD_CACHE_GPTR_TIME_INIT_H__
 
-extern "C"
-{
+#include <fapi2.H>
 
 /// @typedef p9_hcd_cache_gptr_time_initf_FP_t
 /// function pointer typedef definition for HWP call support
-    typedef fapi2::ReturnCode (*p9_hcd_cache_gptr_time_initf_FP_t) (
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+typedef fapi2::ReturnCode (*p9_hcd_cache_gptr_time_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
 
 /// @brief Load GPTR and Time for EX non-core
 ///
@@ -51,7 +54,6 @@ extern "C"
     p9_hcd_cache_gptr_time_initf(
         const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
 
-
-} // extern C
+}
 
 #endif  // __P9_HCD_CACHE_GPTR_TIME_INIT_H__
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
index 6af1cfbe..7c7d2732 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -20,12 +20,6 @@
 /// @file  p9_hcd_cache_initf.C
 /// @brief EX (non-core) scan init
 ///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
 /// Procedure Summary:
 ///   Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
 ///   Check for the presence of cache FUNC override rings from image;
@@ -35,14 +29,18 @@
 ///   (TODO to make sure the image build support is in place)
 ///   Note: all caches that are in the Cache Multicast group will be
 ///   initialized to the same values via multicast scans
-///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
 
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
-#include <fapi2.H>
-//#include <common_scom_addresses.H>
-//will be replaced with real scom address header file
+
 #include "p9_hcd_cache_initf.H"
 
 //------------------------------------------------------------------------------
@@ -53,41 +51,42 @@
 // Procedure: EX (non-core) scan init
 //------------------------------------------------------------------------------
 
-extern "C"
+fapi2::ReturnCode
+p9_hcd_cache_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
+    FAPI_INF(">>p9_hcd_cache_initf");
 
-    fapi2::ReturnCode
-    p9_hcd_cache_initf(
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
-    {
+#ifndef P9_HCD_STOP_SKIP_SCAN
 
-#if 0
-        fapi2::buffer<uint64_t> data;
+    FAPI_DBG("Scanning Cache FUNC Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EQ_FURE,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        // - load_ring ex_lbst_eco conditional_override=1
-        // - load_ring ex_abfa_eco conditional_override=1
-        // - load_ring ex_cmsk_eco conditional_override=1
-        // - load_ring ex_func_perv conditional_override=1
-        // - load_ring ex_func_l3 conditional_override=1
-        // - load_ring ex_func_l3refr conditional_override=1
+    FAPI_DBG("Scanning EX L3 FUNC Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_FURE,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        //Sim Speedup for L3 refresh cycles
-        // - load_ring ex_regf_l3 conditional_override=1
-        // - load_ring ex_regf_l3refr conditional_override=1
+    FAPI_DBG("Scanning EX L2 FUNC Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L2_FURE,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        return fapi2::FAPI2_RC_SUCCESS;
+    FAPI_DBG("Scanning EX L3 Refresh FUNC Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_REFR_FURE,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        FAPI_CLEANUP();
-        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+    FAPI_DBG("Scanning Cache Analog FUNC Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EQ_ANA_FUNC,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-#endif
-
-        return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
 
-    } // Procedure
+#endif
 
+    FAPI_INF("<<p9_hcd_cache_initf");
+    return fapi2::current_err;
+}
 
-} // extern C
 
 
 
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
index 7d5b9914..1c914685 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -20,23 +20,26 @@
 /// @file  p9_hcd_cache_initf.H
 /// @brief EX (non-core) scan init
 ///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
 
 #ifndef __P9_HCD_CACHE_INITF_H__
 #define __P9_HCD_CACHE_INITF_H__
 
-extern "C"
-{
+#include <fapi2.H>
 
 /// @typedef p9_hcd_cache_initf_FP_t
 /// function pointer typedef definition for HWP call support
-    typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) (
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
 
 /// @brief EX (non-core) scan init
 ///
@@ -51,7 +54,6 @@ extern "C"
     p9_hcd_cache_initf(
         const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
 
-
-} // extern C
+}
 
 #endif  // __P9_HCD_CACHE_INITF_H__
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C
index 8e0eca88..d988d96c 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C
@@ -57,12 +57,14 @@ p9_hcd_cache_poweron(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
     FAPI_INF(">>p9_hcd_cache_poweron");
+    fapi2::buffer<uint64_t> l_data64;
 
     //--------------------------
-    // Prepare to cache power on
+    // Prepare to power on cache
     //--------------------------
 
-    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("Drop chiplet enable via NET_CTRL0[0]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(0)));
 
     FAPI_DBG("Assert PCB fence via NET_CTRL0[25]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(25)));
@@ -70,13 +72,13 @@ p9_hcd_cache_poweron(
     FAPI_DBG("Assert chiplet electrical fence via NET_CTRL0[26]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(26)));
 
-    FAPI_DBG("Assert Vital Thold via NET_CTRL0[16]");
+    FAPI_DBG("Assert vital thold via NET_CTRL0[16]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(16)));
 
-    FAPI_DBG("Set L2 glsmux reset via EXCLK_GRID_CTRL[32:33]");
+    FAPI_DBG("Assert L2 glsmux reset via EXCLK_GRID_CTRL[32:33]");
     FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, MASK_OR(32, 2, 0x3)));
 
-    FAPI_DBG("Set L3 glsmux reset via CLOCK_GRID_CTRL[0]");
+    FAPI_DBG("Assert cache glsmux reset via CLOCK_GRID_CTRL[0]");
     FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(0)));
 
     //-----------------------
@@ -89,6 +91,5 @@ p9_hcd_cache_poweron(
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_cache_poweron");
-
     return fapi2::current_err;
 }
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H
index b7091afe..c2037470 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H
@@ -19,6 +19,7 @@
 ///
 /// @file  p9_hcd_cache_poweron.H
 /// @brief Cache Chiplet Power-on
+///
 
 // *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C
index 189e308d..59b89ab6 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -20,25 +20,24 @@
 /// @file  p9_hcd_cache_repair_initf.C
 /// @brief Load Repair ring for EX non-core
 ///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
 /// Procedure Summary:
 ///   Load cache ring images from MVPD
 ///   These rings must contain ALL chip customization data.
 ///   This includes the following:  Repair Power headers, and DTS
-///   Historically this was stored in MVPD keywords are #R, #G. Still stored in ///     MVPD, but SBE image is customized with rings for booting cores
-///
+///   Historically this was stored in MVPD keywords are #R, #G. Still stored in
+///     MVPD, but SBE image is customized with rings for booting cores
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
 
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
-#include <fapi2.H>
-//#include <common_scom_addresses.H>
-//will be replaced with real scom address header file
+
 #include "p9_hcd_cache_repair_initf.H"
 
 //------------------------------------------------------------------------------
@@ -49,33 +48,37 @@
 // Procedure: Load Repair ring for cache
 //------------------------------------------------------------------------------
 
-extern "C"
+fapi2::ReturnCode
+p9_hcd_cache_repair_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
+    FAPI_INF(">>p9_hcd_cache_repair_initf");
 
-    fapi2::ReturnCode
-    p9_hcd_cache_repair_initf(
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
-    {
+#ifndef P9_HCD_STOP_SKIP_SCAN
 
-#if 0
-        fapi2::buffer<uint64_t> data;
+    FAPI_DBG("Scanning Cache REPAIR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EQ_REPR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        // scan chiplet specific ring content
-        FAPI_DBG("Scanning EX REPAIR rings...")
-        // - load_ring_vec_ex ex_repr_eco
+    FAPI_DBG("Scanning EX L3 REPAIR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_REPR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        return fapi2::FAPI2_RC_SUCCESS;
+    FAPI_DBG("Scanning EX L2 REPAIR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L2_REPR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-        FAPI_CLEANUP();
-        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+    FAPI_DBG("Scanning EX L3 Refresh REPAIR Rings");
+    FAPI_TRY(fapi2::putRing(i_target, EX_L3_REFR_REPR,
+                            fapi2::RING_MODE_HEADER_CHECK));
 
-#endif
-
-        return fapi2::FAPI2_RC_SUCCESS;
+fapi_try_exit:
 
-    } // Procedure
+#endif
 
+    FAPI_INF("<<p9_hcd_cache_repair_initf");
+    return fapi2::current_err;
+}
 
-} // extern C
 
 
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H
index db6adf7c..25c71b15 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -20,24 +20,26 @@
 /// @file  p9_hcd_cache_repair_initf.H
 /// @brief Load Repair ring for EX non-core
 ///
-/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
-/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
-/// *HWP Team        : PM
-/// *HWP Consumed by : SBE:SGPE
-/// *HWP Level       : 1
-///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
 
 #ifndef __P9_HCD_CACHE_REPAIR_INITF_H__
 #define __P9_HCD_CACHE_REPAIR_INITF_H__
 
-extern "C"
-{
+#include <fapi2.H>
 
 /// @typedef p9_hcd_cache_repair_initf_FP_t
 /// function pointer typedef definition for HWP call support
-    typedef fapi2::ReturnCode (*p9_hcd_cache_repair_initf_FP_t) (
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+typedef fapi2::ReturnCode (*p9_hcd_cache_repair_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
 
+extern "C"
+{
 
 /// @brief Load Repair ring for EX non-core
 ///
@@ -52,7 +54,6 @@ extern "C"
     p9_hcd_cache_repair_initf(
         const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
 
-
-} // extern C
+}
 
 #endif  // __P9_HCD_CACHE_REPAIR_INITF_H__
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
index 373bc31d..644cb31d 100644
--- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
+++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
@@ -55,6 +55,7 @@
 // Includes
 //------------------------------------------------------------------------------
 
+#include <p9_misc_scom_addresses.H>
 #include <p9_quad_scom_addresses.H>
 #include <p9_hcd_common.H>
 #include "p9_hcd_cache_startclocks.H"
@@ -77,171 +78,183 @@ fapi2::ReturnCode
 p9_hcd_cache_startclocks(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
-    fapi2::buffer<uint64_t> l_data64;
-    uint32_t                l_timeout;
-
     FAPI_INF(">>p9_hcd_cache_startclocks");
+    fapi2::buffer<uint64_t>                     l_qcsr;
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint64_t                                    l_l2sync_clock;
+    uint64_t                                    l_region_clock;
+    uint32_t                                    l_timeout;
+    uint32_t                                    l_attr_system_id     = 0;
+    uint8_t                                     l_attr_group_id      = 0;
+    uint8_t                                     l_attr_chip_id       = 0;
+    uint8_t                                     l_attr_chip_unit_pos = 0;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV>      l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID,  l_chip,
+                           l_attr_group_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID,   l_chip,
+                           l_attr_chip_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip,
+                           l_attr_system_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,         l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET;
+
+    FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_qcsr));
+    FAPI_DBG("Working on cache[%d], good EXs in QCSR[%016llX]",
+             l_attr_chip_unit_pos, l_qcsr);
+
+    // -----------------------------
+    // Prepare to start cache clocks
+    // -----------------------------
+
+    l_region_clock = p9hcd::CLK_REGION_ALL_BUT_EX_DPLL;
+    l_l2sync_clock = 0;
+
+    if (l_qcsr & BIT64(l_attr_chip_unit_pos << 1))
+    {
+        l_region_clock |= p9hcd::CLK_REGION_EX0_L2_L3_REFR;
+        l_l2sync_clock |= BIT64(36);
+        FAPI_DBG("Sequence EX0 EDRAM enables via QPPM_QCCR[0-3]");
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(0)));
+        FAPI_TRY(fapi2::delay(12000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(1)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(2)));
+        FAPI_TRY(fapi2::delay(4000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(3)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+    }
 
-    // -------------------------------
-    // Prepare to cache startclocks
-    // -------------------------------
+    if (l_qcsr & BIT64((l_attr_chip_unit_pos << 1) + 1))
+    {
+        l_region_clock |= p9hcd::CLK_REGION_EX1_L2_L3_REFR;
+        l_l2sync_clock |= BIT64(37);
+        FAPI_DBG("Sequence EX1 EDRAM enables via QPPM_QCCR[4-7]");
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(4)));
+        FAPI_TRY(fapi2::delay(12000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(5)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(6)));
+        FAPI_TRY(fapi2::delay(4000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(7)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+    }
 
-    FAPI_DBG("Enable L3 EDRAM/LCO setup on both EXs");
-    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_OR(23, 2, 0x3)));
-    // 0x0 -> 0x8 -> 0xC -> 0xE -> 0xF to turn on edram
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(0)));
-    FAPI_TRY(fapi2::delay(12000, 200));
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(1)));
-    FAPI_TRY(fapi2::delay(1000, 200));
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(2)));
-    FAPI_TRY(fapi2::delay(4000, 200));
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(3)));
-    FAPI_TRY(fapi2::delay(1000, 200));
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(4)));
-    FAPI_TRY(fapi2::delay(12000, 200));
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(5)));
-    FAPI_TRY(fapi2::delay(1000, 200));
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(6)));
-    FAPI_TRY(fapi2::delay(4000, 200));
-    FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(7)));
-    FAPI_TRY(fapi2::delay(1000, 200));
-
-    FAPI_DBG("Setup OPCG_ALIGN Register");
+    FAPI_DBG("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]");
     FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
     l_data64.insertFromRight<0, 4>(0x5).
     insertFromRight<12, 8>(0x0).
     insertFromRight<52, 12>(0x10);
     FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
 
-    /// @todo partial good information via attribute, drop all fences for now
-    FAPI_DBG("Drop partial good fence via CPLT_CTRL1");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, 0xFFFF700000000000));
+    FAPI_DBG("Drop partial good fences via CPLT_CTRL1[3-14]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, l_region_clock));
 
     FAPI_DBG("Drop vital fence via CPLT_CTRL1[3]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(3)));
 
-    FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3)));
+    FAPI_DBG("Assert EX-L2 clock sync enables via QPPM_EXCGCR[36,37]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, l_l2sync_clock));
 
-    /// @todo set fabric node/chip ID values(read from nest chiplet)
-    // FAPI_DBG("setup fabric group/unit/sys ids");
-    // FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0, <attributes>))
+    FAPI_DBG("Poll for EX-L2 clock sync dones via QPPM_QACSR[36,37]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CACHE_CLK_SYNC_TIMEOUT_IN_MS;
 
-    // -------------------------------
-    // Align Chiplets
-    // -------------------------------
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_QPPM_QACSR, l_data64));
+    }
+    while(((l_data64 & l_l2sync_clock) != l_l2sync_clock) &&
+          ((--l_timeout) != 0));
 
-    FAPI_DBG("Set flushmode_inhibit via CPLT_CTRL0[2]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2)));
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_CACHECLKSYNC_TIMEOUT().set_EQPPMQACSR(l_data64),
+                "EX-L2 Clock Sync Timeout");
+    FAPI_DBG("EX-L2 clock sync done");
 
-    FAPI_DBG("Set force_align via CPLT_CTRL0[3]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(3)));
+    FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3)));
 
-    /// @todo wait for how long
-    /*
-        FAPI_DBG("Poll for cache chiplet aligned");
-        l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
-                    CACHE_CLK_START_TIMEOUT_IN_MS;
-
-        do
-        {
-            FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
-        }
-        while(((l_data64 & BIT64(9)) != 0) && ((--l_timeout) != 0));
-
-        FAPI_ASSERT((l_timeout != 0),
-                    fapi2::PMPROC_CACHECPLTALIGN_TIMEOUT()
-                    .set_EQCPLTSTAT0(l_data64),
-                    "Cache Chiplets Aligned Timeout");
-        FAPI_DBG("Cache chiplets aligned now");
-    */
-    FAPI_DBG("Clear force_align via CPLT_CTRL0[3]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(3)));
+    FAPI_DBG("Set fabric group ID[%x] chip ID[%x] system ID[%x]",
+             l_attr_group_id, l_attr_chip_id, l_attr_system_id);
+    FAPI_TRY(getScom(i_target, EQ_CPLT_CONF0, l_data64));
+    l_data64.insertFromRight<48, 4>(l_attr_group_id).
+    insertFromRight<52, 3>(l_attr_chip_id).
+    insertFromRight<56, 5>(l_attr_system_id);
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0, l_data64));
 
     // -------------------------------
-    // Start Cache Clock
+    // Align chiplets
     // -------------------------------
 
-    FAPI_DBG("Set all bits to zero prior clock start via SCAN_REGION_TYPE");
-    FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
-
-    FAPI_DBG("Start clock(arrays+nsl clock region) via CLK_REGION");
-    l_data64 = p9hcd::CLK_START_REGION_ALL_BUT_DPLL_L2_THOLD_NSL_ARY;
-    FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
+    FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2)));
 
-    /// @todo parameterize delay
-    FAPI_TRY(fapi2::delay(0, 1000000));
+    FAPI_DBG("Assert force_align via CPLT_CTRL0[3]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(3)));
 
-    FAPI_DBG("Start clock(sl+refresh clock region) via CLK_REGION");
-    l_data64 = p9hcd::CLK_START_REGION_ALL_BUT_DPLL_L2_THOLD_ALL;
-    FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
+    FAPI_DBG("Set then unset clear_chiplet_is_aligned via SYNC_CONFIG[7]");
+    FAPI_TRY(getScom(i_target, EQ_SYNC_CONFIG, l_data64));
+    FAPI_TRY(putScom(i_target, EQ_SYNC_CONFIG, DATA_SET(7)));
+    FAPI_TRY(putScom(i_target, EQ_SYNC_CONFIG, DATA_UNSET(7)));
 
-    FAPI_DBG("Poll for L3 clock running");
+    FAPI_DBG("Poll for cache chiplet aligned");
     l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
                 CACHE_CLK_START_TIMEOUT_IN_MS;
 
-    // Read Clock Status Register (Cache chiplet)
-    // check for bits 4:14 eq. zero, no tholds on
     do
     {
-        FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
+        FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
     }
-    while(((l_data64 & (BITS64(4, 4) | BITS64(10, 4))) != 0) && ((--l_timeout) != 0));
+    while((l_data64.getBit<9>() != 1) && ((--l_timeout) != 0));
 
     FAPI_ASSERT((l_timeout != 0),
-                fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCLKSTAT(l_data64),
-                "Cache Clock Start Timeout");
-    FAPI_DBG("Cache clock running now");
+                fapi2::PMPROC_CACHECPLTALIGN_TIMEOUT()
+                .set_EQCPLTSTAT0(l_data64),
+                "Cache Chiplets Aligned Timeout");
+    FAPI_DBG("Cache chiplets aligned now");
+
+    FAPI_DBG("Drop force_align via CPLT_CTRL0[3]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(3)));
+
+    FAPI_TRY(fapi2::delay(0, 900));
 
     // -------------------------------
-    // Start L2 Clock
+    // Start cache clocks
     // -------------------------------
 
-    FAPI_DBG("Raise L2 clock sync enable");
-    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, MASK_OR(36, 2, 3)));
-
-    FAPI_DBG("Poll for clock sync done to raise on EX L2s");
-    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
-                CACHE_CLK_SYNC_TIMEOUT_IN_MS;
-    /*
-    do
-    {
-        FAPI_TRY(getScom(i_target, EQ_QPPM_QACSR, l_data64));
-    }
-    while(((l_data64 & 0x3) != 3) && ((--l_timeout) != 0));
-    */
-    FAPI_ASSERT((l_timeout != 0),
-                fapi2::PMPROC_CACHECLKSYNC_TIMEOUT().set_EQPPMQACSR(l_data64),
-                "L2 Clock Sync Timeout");
-    FAPI_DBG("EX L2s clock sync done");
+    FAPI_DBG("Clear all bits prior start cache clocks via SCAN_REGION_TYPE");
+    FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
 
-    FAPI_DBG("Start clock(arrays+nsl clock region) via CLK_REGION");
-    l_data64 = p9hcd::CLK_START_REGION_L2_THOLD_NSL_ARY;
+    FAPI_DBG("Start cache clocks(arrays+nsl clock region) via CLK_REGION");
+    l_data64 = p9hcd::CLK_START_REGION_NONE_THOLD_NSL_ARY | l_region_clock;
     FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
 
     /// @todo parameterize delay
     FAPI_TRY(fapi2::delay(0, 1000000));
 
-    FAPI_DBG("Start clock(sl+refresh clock region) via CLK_REGION");
-    l_data64 = p9hcd::CLK_START_REGION_L2_THOLD_ALL;
+    FAPI_DBG("Start cache clocks(sl+refresh clock region) via CLK_REGION");
+    l_data64 = p9hcd::CLK_START_REGION_NONE_THOLD_ALL | l_region_clock;
     FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
 
-    FAPI_DBG("Poll for L2 clock running");
+    FAPI_DBG("Poll for cache clocks running via CLOCK_STAT_SL[4-14]");
     l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
                 CACHE_CLK_START_TIMEOUT_IN_MS;
 
-    // Read Clock Status Register (Cache chiplet)
-    // check for bits 4:14 eq. zero, no tholds on
     do
     {
         FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
     }
-    while(((l_data64 & BITS64(8, 2)) != 0) && ((--l_timeout) != 0));
+    while(((l_data64 & l_region_clock) != 0) && ((--l_timeout) != 0));
 
     FAPI_ASSERT((l_timeout != 0),
                 fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCLKSTAT(l_data64),
-                "L2 Clock Start Timeout");
-    FAPI_DBG("L2 clock running now");
+                "Cache Clock Start Timeout");
+    FAPI_DBG("Cache clocks running now");
 
     // -------------------------------
     // Cleaning up
@@ -250,6 +263,7 @@ p9_hcd_cache_startclocks(
     FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]");
     FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(18)));
 
+    /// @todo ignore xstop checkstop in sim, review for lab
     /*
     FAPI_DBG("Check the Global Checkstop FIR");
     FAPI_TRY(getScom(i_target, EQ_XFIR, l_data64));
@@ -257,18 +271,13 @@ p9_hcd_cache_startclocks(
                 fapi2::PMPROC_CACHE_XSTOP().set_EQXFIR(l_data64),
                 "Cache Chiplet Checkstop");
     */
-    FAPI_DBG("Clear flushmode_inhibit via CPLT_CTRL0[2]");
+
+    FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]");
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2)));
 
 fapi_try_exit:
 
     FAPI_INF("<<p9_hcd_cache_startclocks");
-
     return fapi2::current_err;
 }
 
-
-
-
-
-