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| author | Joe McGill <jmcgill@us.ibm.com> | 2016-07-12 23:44:38 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-07-20 23:14:00 -0400 |
| commit | 1360676bf7e29b88614ecdd38e78b3657ceeaabc (patch) | |
| tree | 9d748c3ec4df8ac4d1f09ada761bee71b897b51e /import/chips/p9/procedures/hwp/cache | |
| parent | 346fe8219631d5caea613514d66570b25eaa3639 (diff) | |
| download | talos-sbe-1360676bf7e29b88614ecdd38e78b3657ceeaabc.tar.gz talos-sbe-1360676bf7e29b88614ecdd38e78b3657ceeaabc.zip | |
VBU IPL -- update sim PLL configuration
Adjust refclock/PLL configuration to drive all mesh clocks from PLLs
non-IO/wafer configuration (nest PLL bucket #1) -- default for sc/sq/fc
IO/system model configuration (nest PLL bucket #2) -- default for mc
Regression framework updates
Remove dependence on sim-only varosc/refclock HWPs
Scan from HW image (ultimately need to move to SEEPROM)
Add memory attribute HWPs missing from flow
Handle real/broadside scan options
HWP updates
Scan PLL configuration from image
Preserve clock mux attribute programming
First crack at removing unneeded PLL buckets from images/TOR
Add boot support for warm IPL
Change-Id: Ic7f27ab3dfdf258471d91618adc8eae4cadb2e42
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26938
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26990
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/cache')
| -rw-r--r-- | import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C index 80e757db..8e3b8723 100644 --- a/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C +++ b/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C @@ -55,19 +55,10 @@ p9_hcd_cache_dpll_initf( { FAPI_INF(">>p9_hcd_cache_dpll_initf"); -#ifndef P9_HCD_STOP_SKIP_SCAN - FAPI_DBG("Scanning Cache DPLL FUNC Rings"); - FAPI_TRY(fapi2::putRing(i_target, eq_dpll_func, - fapi2::RING_MODE_HEADER_CHECK)); + FAPI_TRY(fapi2::putRing(i_target, eq_dpll_func)); fapi_try_exit: - -#endif - FAPI_INF("<<p9_hcd_cache_dpll_initf"); return fapi2::current_err; } - - - |
